欢迎访问ic37.com |
会员登录 免费注册
发布采购

SPT574CCS 参数 Datasheet PDF下载

SPT574CCS图片预览
型号: SPT574CCS
PDF下载: 下载PDF文件 查看货源
内容描述: 快速,完整12 - MP位兼容A / D与采样/保持转换器 [FAST, COMPLETE 12-BIT mP COMPATIBLE A/D CONVERTER WITH SAMPLE/HOLD]
分类和应用: 转换器光电二极管
文件页数/大小: 12 页 / 198 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
 浏览型号SPT574CCS的Datasheet PDF文件第2页浏览型号SPT574CCS的Datasheet PDF文件第3页浏览型号SPT574CCS的Datasheet PDF文件第4页浏览型号SPT574CCS的Datasheet PDF文件第5页浏览型号SPT574CCS的Datasheet PDF文件第6页浏览型号SPT574CCS的Datasheet PDF文件第7页浏览型号SPT574CCS的Datasheet PDF文件第8页浏览型号SPT574CCS的Datasheet PDF文件第9页  
SPT574
FAST, COMPLETE 12-BIT
µ
P COMPATIBLE
A/D CONVERTER WITH SAMPLE/HOLD
FEATURES
• Improved Version of the HADC574Z
• Complete 12-Bit A/D Converter with Sample/Hold,
Reference and Clock
• Low Power Dissipation (100 mW Max)
• 12-Bit Linearity (Over Temp)
• 25
µs
Max Conversion Time
• Single +5 V Supply
• Full Bipolar and Unipolar Input Range
APPLICATIONS
Data Acquisition Systems
8 or 12-Bit
µP
Input Functions
Process Control Systems
Test and Scientific Instruments
Personal Computer Interface
GENERAL DESCRIPTION
The SPT574 is a complete, 12-bit successive approximation
A/D converter manufactured in CMOS technology. The de-
vice is an improved version of the HADC574Z. Included on
chip are an internal reference, clock, and a sample-and-hold.
The S/H is an additional feature not available on similar
devices.
The SPT574 features 25
µs
(max) conversion time of 10 or
20 V input signals. Also, a three-state output buffer is added
for direct interface to an 8, 12, or 16-bit
µP
bus.
The SPT574 has standard bipolar and unipolar input ranges
of 10 V and 20 V that are controlled by a bipolar offset pin and
laser trimmed for specified linearity, gain and offset accuracy.
The power supply is +5 V. The device also has an optional
mode control voltage which may be used depending on the
application. With a maximum dissipation of 100 mW at the
specified voltages, power consumption is about five times
lower than that of currently available devices.
The SPT574 is available in 28-lead ceramic sidebrazed DIP,
PDIP and SOIC packages in the commercial temperature
range.
BLOCK DIAGRAM
Nibble A
Output
Nibble B
Three-State Buffers And Control
Nibble C
STS
12-Bit SAR
+
Comp
Clock
12-Bit
Capacitance
DAC
-
Offset/Gain
Trim
Control Logic
Ref
20 V In
10 V In
BIP Off
12/8
CS
Ao
R/C
CE
Ref Out
AGND