Figure 2 – Typical Interface Circuit 2 (PGA and Cerquad packages only)
*See below
+
U1
Voltage
Limiter
V
CC
+
U1
V
EE
22
V
CC
10
W
Q1
Analog
Input
Force
R
T
DGND AGND
L
V
EE
2.2 µF
.01 µF
5.2 V
D1
V
RTF
V
IN
LINV
MINV
2.2 µF
.01 µF
V
RTS
Preamp
Comparator
256
Clock
Buffer
192
MSB
D7
Overrange
D8
Typical Voltage Limiter
RS
49.9
D1
5.2
191
D2
R
+
U1 and U2=
Rail-to-Rail Op Amp
D1=HP, 1N5712
Q1=1N2222A
Q2=1N2907A
R = 1 kW, .1%
U2
10-25
W
V
R3
D6
.01 µF
151
D5
R
10-25
W
V
+
R2
U2
.01 µF
R
128
256 to
8-Bit
Encoder
ECL
Latches
And
Buffers
D4
127
D3
64
D2
.01 µF
63
D1
R
2
LSB
D0
V
REF
2 V
+
U2
22
W
V
RBF
V
RBS
.01 µF
+
U2
10-25
W
V
R1
V
EE
1
V
EE
.01 µF
2.2 µF
DRINV
DREAD
2
AGND
V
EE
50
W
AGND
2 V
.01 µF
5.2 V
V
EE
.01 µF
2 V (Digital)
.01 µF
50
W
CLK
Convert
100116
50
W
50
W
2 V
(Analog)
CLK
Analog Input V
IN
(Sense)
.01 µF
double-sided PC board with a ground plane on the compo-
nent side separated into digital and analog sections will
give the best performance. The converter is bonded-out to
place the digital pins on the left side of the package and
the analog pins on the right side. Additionally, an RF bead
connection through a single point from the analog to digi-
tal ground planes will reduce ground noise pickup.
The circuit in figure 2 (PGA and cerquad packages only) is
intended to show the most elaborate method of achieving
the least error by correcting for integral nonlinearity, input
induced distortion, and power supply/ground noise. This is
achieved by the use of external reference ladder tap con-
nections, an input buffer, and supply decoupling. The func-
tion of each pin and external connections to other compo-
nents is as follows:
V
EE
, AGND, DGND
V
EE
is the supply pin with AGND as ground for the device.
The power supply pins should be bypassed as close to the
device as possible with at least a .01 µF ceramic capaci-
tor. A 1 µF tantalum should also be used for low frequency
suppression. DGND is the ground for the ECL outputs and
is to be referenced to the output pulldown voltage and
appropriately bypassed as shown in figure 1.
V
IN
(ANALOG INPUT)
There are two analog input pins that are tied to the same
point internally. Either one may be used as an analog input
sense
and the other for input
force.
This is convenient for
testing the source signal to see if there is sufficient drive
capability. The pins can also be tied together and driven by
SPT7725
6
8/17/01
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
