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SPT7750AIK 参数 Datasheet PDF下载

SPT7750AIK图片预览
型号: SPT7750AIK
PDF下载: 下载PDF文件 查看货源
内容描述: 8 - BIT , 500 MSPS ,FLASH A / D转换器 [8-BIT, 500 MSPS, FLASH A/D CONVERTER]
分类和应用: 转换器
文件页数/大小: 8 页 / 199 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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SPT7750
8-BIT, 500 MSPS, FLASH A/D CONVERTER
OCTOBER 2002
FEATURES
1:2 Demuxed ECL compatible outputs
Wide input bandwidth – 900 MHz
Low input capacitance – 15 pF
Metastable errors reduced to 1 LSB
Monolithic for low cost
Gray code output
APPLICATIONS
Digital oscilloscopes
Transient capture
Radar, EW, ECM
Direct RF down-conversion
GENERAL DESCRIPTION
The SPT7750 is a full parallel (flash) analog-to-digital con-
verter capable of digitizing full scale (0 to –2 V) inputs into
eight-bit digital words at an update rate of 500 MSPS. The
ECL-compatible outputs are demultiplexed into two sepa-
rate output banks, each with differential data ready out-
puts to ease the task of data capture. The SPT7750’s wide
input bandwidth and low capacitance eliminate the need
for external track-and-hold amplifiers for most applica-
tions. A proprietary decoding scheme reduces metastable
errors to the 1 LSB level. The SPT7750 operates from a
single –5.2 V supply, with a nominal power dissipation of
5.5 W.
The SPT7750 is available in an 80-lead surface-mount
MQuad package over the industrial temperature range
(–25
°C
to +85
°C).
BLOCK DIAGRAM
V
RT
Analog
Input
Preamp
Comparator
256
CLK CLK
CLOCK
BUFFER
DEMUX
CLOCK
BUFFER
255
D8
(OVR)
D7
(MSB)
D6
DRB (DATA READY)
D8B
D7B
D6B
D5B
D4B
D3B
D2B
DRB (DATA READY)
D8B (OVR)
D7B (MSB)
D5B
D6B
152
256 TO 8 Bit Decoder
With Metastable Error Correction
ECL Output Buffers And Latches
151
D4B
D3B
D2B
D1B
D0B (LSB)
DRA (DATA READY)
DRA (DATA READY)
D8A (OVR)
D7A (MSB)
D5A
D4A
D3A
D2A
D1A
D0A (LSB)
D6A
D5
1:2 DEMULTIPLEXER
128
D1B
D0B
V
RM
127
D4
D8A
D7A
D6A
D5A
D4A
D3A
D2A
D1A
D0A
64
D3
63
D2
2
D1
1
D0
(LSB)
V
RB
BANK A
BANK B