TYPICAL INTERFACE CIRCUIT
The SPT7824 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT7824 in
normal circuit operation. The following section provides a
description of the pin functions and outlines critical perfor-
mance criteria to consider for achieving the optimal device
performance.
POWER SUPPLIES AND GROUNDING
The SPT7824 requires -5.2 V and +5 V analog supply
voltages. The +5 V supply is common to analog V
CC
and
digital DV
CC
. A ferrite bead in series with each supply line is
intended to reduce the transient noise injected into the analog
V
CC
. These beads should be connected as closely as pos-
sible to the device. The connection between the beads and
the SPT7824 should not be shared with any other device.
Each power supply pin should be bypassed as closely as
possible to the device. Use 0.1
µF
for V
EE
and V
CC
, and
0.01
µF
for DV
CC
(chip caps are preferred).
Figure 2 - Typical Interface Circuit
R1
CLK
(TTL)
CLK
AGND and DGND are the two grounds available on the
SPT7824. These two internal grounds are isolated on the
device. The use of ground planes is recommended to achieve
optimum device performance. DGND is needed for the DV
CC
return path (40 mA typical) and for the return path for all digital
output logic interfaces. AGND and DGND should be sepa-
rated from each other and connected together only at the
device through a ferrite bead.
A Schottky or hot carrier diode connected between AGND
and V
EE
is required. The use of separate power supplies
between V
CC
and DV
CC
is not recommended due to potential
power supply sequencing latch-up conditions. Using the
recommended interface circuit shown in figure 2 will provide
optimum device performance for the SPT7824.
100
Ω
VIN
(±2 V)
±
2.5 V Max
VIN
COARSE
A/D
4
D10 (Overrange)
D9 (MSB)
D I G IT A L O U
DECODING NETWORK
+5V
C19
1
µF
2
+
VIN
IC1
6
VOUT
+2.5 V
VFT
D8
D7
D6
D5
D4
D3
D2
D1
(REF-03)
4
GND
5
10 kΩ
+
1
µF
30 kΩ
Trim
C1
.01
µF
C2
.01
µF
VST
R
ANALOG
PRESCALER
2R
C3
.01
µF
VRM
2R
2R
2R
3
1
10 kΩ
2
4
+ -
IC2
OP-07
8
7
- 5.2 V
SUCCESSIVE
INTERPOLATION
STAGE # 1
.01
µF
30 kΩ
+5 V
.01
µF
C4
.01
µF
VSB
D0 (LSB)
R
SUCCESSIVE
INTERPOLATION
STAGE # N
6
-2.5 V
VFB
VCC
+
VCC
VEE
VEE
1
µF
AGND
C6
.1
µF
C7
.1
µF
C8
C9
C10
.01
µF
C11
.01
µF
Notes to prevent latch-up due to power sequencing:
FB
1)
D1 = Schottky or hot carrier diode, P/N IN5817.
D1
2)
FB = Ferrite bead, Fair Rite P/N 2743001111
10
µF
to be mounted as close to the device as possible. The ferrite bead to the
ADC connection should not be shared with any other device.
3)
C1-C11 = Chip cap (recommended) mounted as close to the device's pin
as possible.
4)
Use of a separate supply for VCC and DVCC is not recommended.
-5.2 V
(Analog)
5)
R1 provides current limiting to 45 mA.
6)
C6, C7, C8 and C9 should be ten times larger than C10 and C11.
7)
C8 = C9 = a 0.1
µF
cap in parallel with a 4.7
µF
cap.
10
µF
+
+
FB
AGND
+5 V
(Analog)
FB
DGND
DGND
AGND
DVCC
DVCC
C5
.01
µF
DGND
SPT7824
6
3/11/97
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
