ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
Output
Digital Outputs .......................................... +30 to -30 mA
V
CC
V
EE
...........................................................................+6 V
........................................................................... -6 V
Temperature
Input Voltages
Analog Input............................................... V ≤V ≤V
Operating Temperature ............................ -55 to +125 °C
Junction Temperature .............................................. +175 °C
Lead Temperature, (soldering 10 seconds) ........ +300 °C
Storage Temperature................................ -65 to +150 °C
1
FB IN FT
, V ..............................................................+3.0 V, -3.0 V
V
FT FB
Reference Ladder Current .....................................12 mA
CLK Input .................................................................. V
CC
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T =T
A
- T
, V =+5.0 V, V =-5.2 V, DV =+5.0 V, V =±2.0 V, V =-2.0 V, V =+2.0 V, f
=40 MHz, 50% clock duty cycle, unless otherwise
CLK
MIN
MAX CC
EE
CC
IN
SB
ST
specified.
TEST
CONDITIONS
TEST
LEVEL
SPT7824A
TYP
SPT7824B
TYP MAX UNITS
PARAMETERS
MIN
MAX
MIN
Resolution
10
10
Bits
±
DC Accuracy (+25 °C)
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
Full Scale
100 kHz Sample Rate
V
V
±1.0
±0.5
±1.5
±0.75
LSB
LSB
VI
Guaranteed
Guaranteed
Analog Input
f
=1 MHz
=0 V
CLK
Input Voltage Range
Input Bias Current
Input Bias Current
Input Resistance
Input Resistance
Input Capacitance
Input Bandwidth
+FS Error
V
VI
IV
VI
IV
V
±2.0
30
±2.0
V
V
60
75
30
60 µA
75 µA
kΩ
IN
T =-55 to +125 °C
A
100
75
300
300
5
100
75
300
300
5
T =-55 to +125 °C
kΩ
pF
A
3 dB Small Signal
V
V
V
120
±2.0
±2.0
120
±2.0
±2.0
MHz
LSB
LSB
-FS Error
Reference Input
f
=1 MHz
CLK
Reference Ladder Resistance
Reference Ladder Tempco
VI
V
500
40
800
0.8
500
800
0.8
Ω
Ω/°C
Timing Characteristics
Maximum Conversion Rate
Overvoltage Recovery Time
Pipeline Delay (Latency)
Output Delay
VI
V
IV
V
V
V
40
14
MHz
ns
20
20
1
18
1
Clock Cycle
T =+25 °C
14
1
5
18 ns
ns
A
Aperture Delay Time
Aperture Jitter Time
Acquisition Time
T =+25 °C
1
5
12
A
T =+25 °C
ps-RMS
ns
A
T =+25 °C
A
V
12
Dynamic Performance
Effective Number of Bits
f
f
f
=1 MHz
=3.58 MHz
=10.0 MHz
8.7
8.7
7.3
8.2
8.2
6.9
Bits
Bits
Bits
IN
IN
IN
Typical thermal impedances (unsoldered, in free air): 28L sidebrazed DIP: θ = 50 °C/W, 28L plastic DIP: θ = 50°C/W,
ja
ja
28L SOIC: θ = 100 °C/W.
ja
SPT7824
2
3/11/97
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
