Figure 9 - Analog Input Track-and-Hold Timing and Reference Settling-and-Hold Timing
Synchronous Mode
*
Single Shot Mode
(
SC
high, no B cycle)
SC
Free Run Mode (
SC
always Ø)
Clock
1
A
2
A
3
A
4
A
13
A
14
A
1
B
2
B
3
B
4
B
V
REF+
Ref Hold
Ref Settling Window
**
A
IN
Sample
Input
Sample
Input
*
The rising edge of the SC line can occur any time between the
rising edge of clock 1A and the falling edge of clock 14A.
**
The reference settling window
can be extended in the
synchronous mode by adding extra clocks between conversion
cycles. The example shown is the minimum number of clocks
required (14) per conversion cycle.
PACKAGE OUTLINE
8-Lead SOIC
INCHES
MIN
MAX
0.187
0.228
0.050 typ
0.014
0.005
0.060
0.055
0.149
0°
0.007
0.016
0.194
0.242
0.019
0.010
0.067
0.060
0.156
8°
0.010
0.035
MILLIMETERS
MIN
MAX
4.80
5.84
1.27 typ
0.35
0.13
1.55
1.40
3.81
0°
0.19
0.41
4.98
6.20
0.49
0.25
1.73
1.55
3.99
8°
0.25
0.89
A
SYMBOL
A
B
C
D
B
E
F
G
H
I
J
K
H
G
F
C
D
E
I
K
J
SPT7830
7
12/29/99
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
