SPT7860
10-BIT, 40 MSPS, 175 mW A/D CONVERTER
TECHNICAL DATA
MAY 25, 2001
FEATURES
• Monolithic 40 MSPS converter
• 175 mW power dissipation
• On-chip track-and-hold
• Single +5 V power supply
• TTL/CMOS outputs
• 5 pF input capacitance
• Low cost
• Tri-state output buffers
• High ESD protection: 3,500 V minimum
• Selectable +3 V or +5 V logic I/O
APPLICATIONS
• All high-speed applications where low power
dissipation is required
• Video imaging
• Medical imaging
• Radar receivers
• IR imaging
• Digital communications
GENERAL DESCRIPTION
The SPT7860 is a 10-bit monolithic, low-cost, ultralow-
power analog-to-digital converter capable of minimum
word rates of 40 MSPS. The on-chip track-and-hold func-
tion assures very good dynamic performance without the
need for external components. The input drive require-
ments are minimized due to the SPT7860’s low input
capacitance of only 5 pF.
Power dissipation is extremely low at only 175 mW typical
at 40 MSPS with a power supply of +5.0 V. The digital out-
puts are +3 V or +5 V, and are user selectable. The
SPT7860 is pin-compatible with an entire family of 10-bit,
CMOS converters (SPT7835/40/50/55/60/61), which sim-
plifies upgrades. The SPT7860 has incorporated propri-
etary circuit design* and CMOS processing technologies
to achieve its advanced performance. Inputs and outputs
are TTL/CMOS-compatible to interface with TTL/CMOS
logic systems. Output data format is straight binary.
The SPT7860 is available in 28-lead SOIC and 32-lead
small (7 mm square) TQFP packages over the commer-
cial temperature range.
*Patent pending
BLOCK DIAGRAM
ADC Section 1
A
IN
1:16
Mux
T/H
Auto-
Zero
CMP
11-Bit
SAR
11
11
D10 Overrange
D9 (MSB)
D8
D7
D6
D5
D4
D3
D2
D1
P1
DAC
CLK In
Timing
and
Control
Enable
.
.
.
P15
P2
P16
.
.
.
ADC Section 15
ADC Section 2
ADC Section 16
T/H
Auto-
Zero
CMP
.
.
.
11-Bit
SAR
11
DAC
11
.
.
.
11
11
11-Bit
16:1
Mux/
Error
Correction
Data
Valid
Ref
In
Reference Ladder
D0 (LSB)
V
REF
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
