Figure 3 - Typical Interface Circuit (Single-Ended Operational Design)
1 µF
(TTL to PECL
Translator)
A+5V
300
0.01 µF
+
1
2
8
7
V
(+3.0 V)
Q0
CC
0.1 µF
10
50
(Optional Level-Shift Circuit)
Q0
Q1
DO
D1
50
3
4
6
5
28
27
1
GND(THA)
CLK
CLK
TTL Clock
(Sample Clock, up to 100 MHz)
XUF (Dependent on Frequency)
Analog In
2
3
GND(THA)
Analog IN
Q1
GND
A+5V
26
AV (THA)
CC
4.7 µF
0.01 µF
50
4
5
GND(SUB)
GND(THA)
25
24
AV (THA)
CC
+
3
2
7
OP191
4
+
-
A+5V
AV (THA)
CC
6
0.1 µF
6
GND(CAP)
23
22
22
AV (THA)
CC
0.01 µF
22
N/C
N/C
N/C
7
8
GND(THA)
GND(THA)
AV (THA)
CC
(+2.5 V)
21
20
19
OUT
OUT+
9
REF IN
INV A
INV B
N/C
0.01 µF
4.7 µF
10
REF OUT
AV (Ref)
CC
18
17
11
A+5V
4.7 µF
OUT-
+
12 GND(Ref)
13 GND(SUB)
AV (INV)
CC
N/C
N/C
16
15
0.01 µF
AV (INV)
CC
14 GND(INV)
AV (ESD)
CC
A+5V
0.01 µF
Notes:
1. Input signal is typically at a +2.5 V offset. The optional level-shift circuit may be eliminated if
driving from a source that already provides for this offset.
2. The device may be operated from -5 V supply on GND pins and 0 V on AV
pins. All input and
CC
output pins will be shifted by -5 V. The use of an ECL level may be used to drive the clock inputs.
3. V
(ESD) is the high voltage for the ESD protection diodes and must be connected in all
applications. NOTE: It should be tied to V (THA), not to V (INV).
CC
CC
CC
Figure 4 - Typical Interface Circuit (Differential Operational Design)
1 µF
(TTL to PECL
Translator)
A+5V
300
0.01 µF
(+3.0 V)
1
2
+
8
7
V
Q0
CC
0.1 µF
10
50
(Optional Level-Shift Circuit)
Q0
Q1
DO
D1
50
3
4
6
5
28
27
1
GND(THA)
CLK
CLK
TTL Clock
XUF (Dependent on Frequency)
(Sample Clock, up to 100 MHz)
Analog In
2
3
GND(THA)
Analog IN
Q1
GND
A+5V
26
AV (THA)
CC
4.7 µF
0.01 µF
50
4
5
GND(SUB)
GND(THA)
25
24
AV (THA)
CC
+
3
2
7
OP191
4
+
-
A+5V
AV (THA)
CC
6
0.1 µF
6
GND(CAP)
23
22
22
AV (THA)
CC
0.01 µF
7
8
GND(THA)
GND(THA)
AV (THA)
CC
(+2.5 V)
21
20
19
OUT+
OUT+
22
+
9
REF IN
INV A
INV B
4.7 µF
10
(Differential Output)
REF OUT
0.01 µF
22
AV (Ref)
CC
18
17
11
A+5V
4.7 µF
OUT-
OUT-
A+5V
+
0.01 µF
12 GND(Ref)
13 GND(SUB)
AV (INV)
CC
+
16
15
0.01 µF
4.7 µF
AV (INV)
CC
14 GND(INV)
AV (ESD)
CC
Notes:
1. Input signal is typically at a +2.5 V offset. The optional level-shift circuit may be eliminated if
driving from a source that already provides for this offset.
2. The device may be operated from -5 V supply on GND pins and 0 V on AV
pins. All input and
CC
output pins will be shifted by -5 V. The use of an ECL level may be used to drive the clock inputs.
3. V
CC
(ESD) is the high voltage for the ESD protection diodes and must be connected in all
applications. NOTE: It should be tied to V
(THA), not to V
(INV).
CC
CC
SPT9110
7
11/12/98
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
