ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
Output Currents
Positive Supply Voltage (VCC)................................ +7 V
Negative Supply Voltage (VEE) .............................. –7 V
A/D Ground Voltage Differential ........................... 0.5 V
Internal Reference Output Current .................... 500 µA
Control Amplifier Output Current .....................±2.5 mA
Temperature
Input Voltages
Digital Input Voltage
(D1–D12, Latch Enable) ............................... 0 V to VCC
Control Amp Input Voltage Range ............... 0 V to –4 V
Reference Input Voltage Range (VREF) ........ 0 V to VEE
Operating Temperature .......................... –40 to +85 °C
Junction Temperature ...................................... +150 °C
Lead, Soldering (10 seconds) ......................... +300 °C
Storage ................................................ –65 to +150 °C
Note: 1. Operation at any Absolute Maximum Rating is not implied.See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
TA = TMIN – TMAX, VCC = +5.0 V, VEE = –5.2 V, RSet = 7.5 kΩ, Control Amp In = Ref Out, VOUT = 0 V, unless otherwise specified.
TEST
CONDITIONS
TEST
SPT9713A
SPT9713B
MIN TYP MAX
PARAMETERS
LEVEL MIN TYP MAX
UNITS
DC Performance
Resolution
12
12
Bits
LSB
LSB
LSB
LSB
pF
% FS
% FS
PPM/°C
µA
Differential Linearity
Differential Linearity
Integral Linearity
Integral Linearity
Output Capacitance
Gain Error1
I
VI
I
VI
V
I
VI
V
I
VI
V
IV
IV
±0.5 ±0.75
±1.5
±0.75 ±1.0
±1.0 ±1.25
±2.0
±1.0 ±1.5
Max at Full Temp.
Best Fit
Max at Full Temp.
+25 °C
±1.75
±2.0
10
1.0
10
1.0
+25 °C
5.0
8.0
5.0
8.0
Full Temp.
Full Temp.
+25 °C
Full Temp.
Full Temp.
+25 °C
Gain Error Tempco
Zero-Scale Offset Error
150
0.5
150
0.5
2.5
5.0
2.5
5.0
µA
µA/°C
V
Offset Drift Coefficient
Output Compliance Voltage
Equivalent Output Resistance
0.01
1.0
0.01
1.0
–1.2
0.8
+2.0
1.2
–1.2
0.8
+2.0
1.2
+25 °C
kΩ
Dynamic Performance
Conversion Rate
+25 °C
+25 °C
+25 °C
+25 °C
+25 °C
+25 °C
2 MHz Span
2 MHz Span
2 MHz Span
10 MHz Span
RL = 50 Ω
IV
V
V
V
V
100
100
MWPS
ns
ns
pV-s
mA
2
Settling Time tST
13
2
15
13
2
15
3
Output Propagation Delay tD
Glitch Energy4
Full Scale Output Current5
Spurious-Free Dynamic Range6
1.23 MHz; 10 MWPS
5.055 MHz; 20 MWPS
10.1 MHz; 50 MWPS
16 MHz; 40 MWPS
20.48
20.48
V
V
V
V
V
70
68
68
68
2
70
68
68
68
2
dBc
dBc
dBc
dBc
ns
Rise Time / Fall Time
1Gain is measured as a ratio of the full-scale current to ISet.The ratio is nominally 128.
2Measured as voltage at mid-scale transition to ±0.024%;RL=50 Ω.
3Measured from the rising edge of Latch Enable to where the output signal has left a 1 LSB error band.
4Glitch is measured as the largest single transient.
5Calculated using IFS = 128 x (Control Amp In / RSet
)
6SFDR is defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output spectrum window,
which is centered at the fundamental frequency and covers the indicated span.
SPT9713
2
2/15/01
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
