TMC2192
PRODUCT SPECIFICATION
Synchronization Modes
Control Registers for this section
Address
0x06
0x06
0x06
Bit(s)
5-3
1
0
Name
MODE
TOUT
TSOUT
CCIR656
The TMC2192 derives all synchronization from the embed-
ded TRS (timing reference signals) information. Blanking of
selected lines is determined by the v bit of the TRS. However
the control registers VBIENx can override and blank the
active video portion of VBI lines regardless of the state of the
v-bit.
Genlock
The TMC2192 offers a variety of synchronization modes;
these are master, slave, genlock, 656 mode, and DRS-Lock.
In master mode, the TMC2192 generates its own timing and
the synchronization is supplied externally by HSOUT and
VSOUT signals. In slave and genlock modes the TMC2192
derives its timing from the input pins HSIN, VSIN. In 656
mode the timing is driven by the synchronization codes
embedded into the data stream.
Master
The TMC2192 is driven by the input synchronization pins
HSIN and VSIN. When the falling edge of HSIN and VSIN
occurs at the same rising edge of PXCK the TMC2192 will
start a new field.VSIN can be either a traditional pulse or the
MPEG style field toggle. In both cases the TMC2192 will
flywheel through fields 2, 4, 6, and 8 synchronizing only to
fields 1, 3, 5, and 7. The TMC2192 collects GRS data and
resets its subcarrier phase and frequency to the data embed-
ded in the GRS stream. The GRS detection occurs only on
the CBVS port.
DRS
The TMC2192 drives the output pins HSOUT and VSOUT
to synchronize the incoming video. A new color frame starts
at the rising edge of RESET. The encoder always starts at the
1
st
vertical serration in field 8 and will freerun the field and
line sequence. The control register bit SRESET can be used
to synchronize the start of the field and line sequence in mas-
ter mode by resetting the FVHGEN state machine. Output
synchronization signal VSOUT can operate in a traditional
sync mode or in a MPEG style field toggle mode.
Slave
The TMC2192 is driven by the input synchronization pins
HSIN and VSIN. When the falling edge of HSIN and VSIN
occurs at the same rising edge of PXCK the TMC2192 will
start a new field.VSIN can be either a traditional pulse or the
MPEG style field toggle. In both cases the TMC2192 will
flywheel through fields 2, 4, 6, and 8 synchronizing only to
fields 1, 3, 5, and 7. Subcarrier phase adjustment is deter-
mined by the DRS data. The DRS detection can occur on
either the CBVS port or the pixel data port.
The TMC2192 is driven by the input synchronization pins
HSIN and VSIN. When the falling edge of HSIN and VSIN
occurs at the same rising edge of PXCK the TMC2192 will
start a new field.VSIN can be either a traditional pulse or the
MPEG style field toggle. In both cases the TMC2192 will
flywheel through fields 2, 4, 6, and 8 synchronizing only to
fields 1, 3, 5, and 7.
Propagation Delay
The propagation delay from the pixel data (PD) input to the
D/A output is 64 PXCK’s. Figure 8 shows the propagation
delay for both master and slave synchronization modes. For
CCIR656 data streams, pixel 736 (pixel 0 in Figure 8) is the
midpoint of sync and is 32 PXCK’s (24 PXCK’s in PAL)
after the EAV TRS.
n = (SY+BR+BU+CBP+AV)*2
0
63
65
128
PXCK
PD[23:14]
C
Bn
Y
n
C
Rn
Y
n+1
C
B0
Y
0
HSIN
t
DO
HSOUT
(TSOUT = 1)
DACx
(ANALOG)
DCVBS
(D[7:0],FLD[2:1])
t
DO
COMP
0
COMP
1
65-6294-09
Midpoint of the
Falling Edge of Sync
Figure 7. Propagation Delay through the Encoder
10
REV. 1.0.0 8/13/03
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
