PRODUCT SPECIFICATION
TMC22071A
Control Register Bit Functions
(continued)
Bit
25
Name
AGC
Function
AGC operation control. After H and V sync acquisition, the A/D converter references are
adjusted to encompass the full video range. The system can initiate an A/D adjustment
sequence at any time by bringing this bit HIGH. The control bit will reset to 0 following
AGC adjustment.
When HIGH, a free-running PXCK is generated, independent of incoming video. When
LOW, PXCK is locked to incoming video.
Factory test control bits. These should be set LOW.
Block sync enable. When HIGH the TMC22071A accepts both normal and block sync.
(In block sync, the incoming signal is at the sync tip level for 2.5 (PAL) or 3 (NTSC)
consecutive lines. Equalization pulses may be absent.) When LOW, only normal sync
may be input. For most applications, whether using a VCR or a studio video input
source, best performance will be found when this bit is HIGH.
CVBS bus enable. When LOW, the CVBS
7-0
, GHSYNC, and GVSYNC outputs are in a
high-impedance state. When HIGH, they are enabled.
Factory test control bit. This should be set LOW.
Burst phase / frequency output control. When HIGH, GRS is disabled. When LOW, burst
phase and frequency information is output on CVBS
3-0
.
Digital clamp enable. The digital clamp is enabled when DCLAMP is HIGH and disabled
when LOW.
Factory test control bits. These should be set LOW.
Sync tip value. When DCLAMP is HIGH and STVAL is set to its default value 3
h
the
output sync level is 3
h
for NTSC and 7
h
for PAL. Bit 43 is the MSB.
VCR lock control. Setting this bit LOW improves the TMC22071A’s locking to VCR
signals. When only clean video input signals are used, the user may set this bit HIGH for
compatibility with existing TMC22071 firmware.
Factory test control bit. This should be set LOW.
When the horizontal phase lock loop becomes unlocked (i.e. after video input is
disconnected) and this Control Bit is HIGH, all CVBS data is forced LOW except
subcarrier frequency and phase data (GRS). GHSYNC, GVSYNC, and PXCK continue
with default GRS data until video is required. The presence of GRS also depends upon
bit 33. If the GRSONLY bit is LOW, GHSYNC, GVSYNC, and PXCK continue with
default GRS data continue but video pixel data is random.
Burst present status bit. This bit is HIGH when burst is present on the input video. It is
LOW, when burst is not present.
Blanking amplitude status bit. These eight bits report the actual blanking level.
H-lock loop status bit. When HIGH, the TMC22071A is not locked to an input signal.
When LOW, lock has been achieved.
These are read-only bits for testing puposes only.
26
27-29
30
FRERUN
TEST
VCR/TV
31
32
33
34
35-39
40-43
44
CVBSEN
TEST
BPFOUT
DCLAMP
TEST
STVAL
VCR
45
46
TEST
GRSONLY
Status Bits (Read Only)
47
48-55
56
57-58
COLOR
BLKAMP
LOCK
TEST
9
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