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TMC22071AR1C 参数 Datasheet PDF下载

TMC22071AR1C图片预览
型号: TMC22071AR1C
PDF下载: 下载PDF文件 查看货源
内容描述: 同步锁相视频数字化 [Genlocking Video Digitizer]
分类和应用: 商用集成电路
文件页数/大小: 24 页 / 227 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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TMC22071A
PRODUCT SPECIFICATION
Pin Assignments
(continued)
80
81
51
50
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16*
17
18
19
20
21
22
23
24
25
Name
A
0
NC
NC
R/W
CS
V
DD
RESET
D
GND
D
0
NC
NC
NC
NC
NC
NC
D
GND
INT
V
DD
NC
NC
CVBS
0
CVBS
1
CVBS
2
CVBS
3
CVBS
4
Pin
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41*
42*
43
44
45
46
47
48
49
50
Name
V
DD
D
GND
CVBS
5
CVBS
6
CVBS
7
NC
GHSYNC
GVSYNC
VALID
NC
NC
NC
D
GND
D
GND
LDV
D
GND
V
DD
NC
V
DD
PXCK
D
GND
D
GND
V
DD
V
DDA
A
GND
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Name
V
DDA
V
DDA
NC
NC
A
GND
NC
R
B
V
IN3
NC
V
DDA
V
IN2
NC
A
GND
V
DDA
V
IN1
NC
A
GND
R
T
A
GND
V
REF
NC
A
GND
V
DDA
A
GND
C
BYP
Pin
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Name
NC
PFD IN
NC
NC
NC
A
GND
DDS OUT
NC
NC
NC
PXCK SEL
V
DDA
COMP
A
GND
D
GND
CLK IN
V
DD
CLK OUT
EXT PXCK
D
GND
D
GND
D
GND
V
DD
NC
V
DD
65-22071-02B
100
1
30
31
Notes:
1. NC = Do Not Connect.
* These pins are not connected in the
TMC22071A. However, you should
connect these pins as shown for
compatibility with future genlock ICs.
Pin Definitions
Pin Number
Pin Name
Video Input
V
IN1-3
Clocks
CLK IN
51
91
CMOS
20 MHz DDS clock input.
20 MHz CMOS clock input to DDS. This
pin may also be used along with CLK OUT for directly connecting
crystals.
Inverted clock output.
Inverted DDS clock output. This pin may also
be used along with CLK IN for directly connecting a crystal.
2x Pixel clock output.
2x oversampled line-locked clock output.
Pixel clock output.
Delayed pixel clock output. LDV runs at 1/2 the
rate of PXCK and its rising edge is useful for transferring CVBS
digital video from the TMC22071A to the TMC22x9x Digital Video
Encoders.
External PXCK input.
Input for external PXCK clock source.
PXCK source select.
Select input for internal or external PXCK.
When HIGH, the internally generated line-locked PXCK is selected.
When LOW, the external PXCK source is enabled.
34, 31,
29
65, 61,
58
1.23Vp-p
Composite Video Input.
Video inputs,1.25 Volts peak-to-peak, sync
tip to peak color
68 pin
PLCC
100 pin
MQFP
Pin Type
Function
CLK OUT
PXCK
LDV
53
19
17
93
45
40
CMOS
CMOS
CMOS
EXT PXCK
PXCK SEL
54
46
94
86
CMOS
CMOS
4