TMC2250A
PRODUCT SPECIFICATION
Pin Descriptions
(continued)
Pin Number
Pin Name CPGA/PPGA/
MPGA
KA
9-0
MQFP
Function
Pin Description
Data presented to the 10-bit registered coefficient
input ports KA, KB and KC are latched three at a time
into the internal coefficient storage register set
indicated by the Coefficient Write Enable CWE
1,0
on
the next clock, as shown in Table 4.
K13, J11, K12, 69, 68, 67, 66, Coefficient
L13, L12, K11, 65, 64, 63, 62, Input A1, A2,
M13, M12,
61, 60
A3
L11, N13
M11, L10,
59, 58, 57, 56, Coefficient
N12, N11, 55, 54, 53, 52, Input B1, B2,
M10, L9, N10,
51, 50
B3
M9, N9, L8
M8, N8, N7, 49, 48, 47, 45, Coefficient
M7, N6, M6, 44, 43, 41, 40, Input B1, B2,
N5, M5, N4, L5
39, 38
B3
KB
9-0
KC
9-0
XC
11-0
YC
11-8
Y
7-4
YC
3-0
ZC
11-0
In all modes except Mode 00, the x port and four bits
of the Y output port are reconfigured as the 16-bit
registered Cascade Input port CASIN
15-0
. Data
presented to this input will be added to the weighted
sums of the data words which were presented to the
D1, E2, E1, F2 9, 10, 11, 13 CASIN
3-0
/
input ports (A, B and C).
Output Y
11-0
In the matrix multiply mode, data are available at the
F1, G2, G1, H1 14, 15, 17, 18 Output
7-4
only 12-bit registered output ports X, Y AND Z t after
DO
K1, J2, J1, H2 23, 22, 21, 19 CASOUT
3-0
/
every clock. These ports are reconfigured in the
Output Y
3-0
filtering modes as 16-bit Cascade Input and Output
M4, N3, M3, 37, 36, 35, 33, CASOUT
15-4
/ ports.CASOUT
15-0
In all modes except Mode 00, the Z port and four bits
N2, M2, L3, 32, 31, 30, 29, Output Z
11-0
of the Y output port are reconfigured as the 16-bit
N1, L2, K3, 28, 27, 26, 25
registered Cascade Output port CASOUT
15-0
.
M1, L1, K2
B4, A3, A2, B3,
115, 116,
CASIN
15-4
/
A1, C3, B2, B1,
117, 119,
Output X
D3, C2, C1, D2 120, 1, 2, 3, 4,
5, 6, 7
Notes:
1. The output ports X, Y, Z and CASOUT, and input port CASIN are internally reconfigured by the device as required for each
mode of the device. The multiple-function pins have names which are combinations of these titles, as appropriate.
2. The output drivers on pins XC
11-0
and YC
11-8
are not necessarily disabled until after the first rising edge of CLK following
power-up. If these pins are to be tied to other output drivers, to each other, or to ground or V
DD
, the user should ensure that
a clock pulse arrives within a few seconds of power-up, to avoid bus contention.
Table 3. Configuration Mode Word
MODE
1,0
00
01
10
11
Configuration Mode
3 x 3 Matrix Multiply
9-Tap One Dimensional FIR
3 x 3 -Pixel Convolver
4 x 2 -Pixel Convolver
Table 4. Coefficient Write Enable Word
CWE
1,0
00
01
10
11
Coefficient Set Selected
Hold all registers
Update KA1, KB1, KC1
Update KA2, KB2, KC2
Update KA3, KB3, KC3
REV. 1.0.2 10/25/00
7
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
