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CM3132-02SH 参数 Datasheet PDF下载

CM3132-02SH图片预览
型号: CM3132-02SH
PDF下载: 下载PDF文件 查看货源
内容描述: 三路线性稳压器为DDR -I内存和CPU [Triple Linear Voltage Regulator for DDR-I Memory and CPU]
分类和应用: 稳压器模拟IC信号电路光电二极管双倍数据速率
文件页数/大小: 11 页 / 227 K
品牌: CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
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PRELIMINARY
CM3132
Triple Linear Voltage Regulator for DDR-I Memory and CPU
Features
Fully integrated power solution for a CPU/SOC
core and DDR-I memory ICs
Lowest system cost and smallest footprint with just
three external output capacitors
Three linear regulators for V
CORE
(1.5A), V
DDQ
(1.5A), and V
TT
(0.5A, source-sink)
Product Description
The CM3132 provides an integrated power solution for a
CPU core and DDR-I memory for consumer and other
embedded applications. It features three independent linear
regulators for V
CORE
, V
DDQ
and V
TT
supply regulation. The
default voltage for V
CORE
is 1.5V. The SENSE_CORE pin
can be tied to GND for the default voltage, or through a
resistor divider for setting the CPU core in the range 1.2V to
1.8V. V
DDQ
is internally set to 2.50V and the V
TT
voltage is
always half the V
DDQ
voltage. A capacitor should be con-
nected to each of the three outputs.
There are two enable pins, EN_CORE and EN_DDR. When
EN_CORE is set high, the CORE regulator is disabled.
When EN_DDR is set high, the two DDR regulators are dis-
abled to minimize overall system power dissipation when
memory is in standby mode. These two enable pins allow
power sequencing of the DDR and CORE regulator blocks
independently.
The CM3132 is available in a PSOP-8 package that has
excellent thermal dissipation.
It is available with optional
lead-free finishing.
V
DDQ
= 2.5V, V
TT
= V
DDQ
/2
±
25mV
V
CORE
is adjustable, with a default output of 1.5V
Over-temperature and reverse current protection
Overcurrent protection for all regulators
PSOP-8 package with integrated heat spreader
Lead-free version available
Applications
Core CPU and DDR-I memory power for:
Set Top Boxes, DVD Players, Games
Digital TVs, Flat Panel Displays
Printers, Digital Projectors
Embedded systems
Communications systems
Typical Application Circuit
2.8V to 3.3V
Circuit Schematic
V
CC
V
REF
V
DDQ
REGULATOR
V
DDQ
V
DDQ
= 2.5V
V
CC
V
DDQ
REGULATOR
C
VCC
V
REF
EN_DDR
Enable DDR
Memory #
EN_DDR
C
DDQ
DDR
MEMORY
R
R
C
TT
V
TT
REGULATOR
V
REF
=1.25V
V
TT
=1.25V
R
R
V
TT
REGULATOR
V
TT
V
REF
V
CORE
REGULATOR
V
CORE
R3
V
REF
CPU
CORE
+ I/O
C
CORE
V
CORE
REGULATOR
V
CORE
Enable CORE#
EN_CORE
SENSE_CORE
R4
EN_CORE
SENSE_CORE
GND
GND
©
2004 California Micro Devices Corp. All rights reserved.
10/13/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
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