PRELIMINARY
CM3202
Application Information (cont’d)
1.22V
CM3202
Application Information
Powering DDR Memory
Double-Data-Rate (DDR) memory has provided a huge
step in performance for personal computers, servers
and graphic systems. As is apparent in its name, DDR
operates at double the data rate of earlier RAM, with
two memory accesses per cycle versus one. DDR
SDRAM's transmit data at both the rising falling edges
of the memory bus clock.
DDR’s use of Stub Series Terminated Logic (SSTL)
topology improves noise immunity and power-supply
rejection, while reducing power dissipation. To achieve
this performance improvement, DDR requires more
complex power management architecture than previ-
ous RAM technology.
Unlike the conventional DRAM technology, DDR
SDRAM uses differential inputs and a reference volt-
age for all interface signals. This increases the data
bus bandwidth, and lowers the system power con-
sumption. Power consumption is reduced by lower
operating voltage, a lower signal voltage swing associ-
ated with Stub Series Terminated Logic (SSTL_2) and
by the use of a termination voltage, V
TT
. SSTL_2 is an
©
2006 California Micro Devices Corp. All rights reserved.
05/08/06
industry standard, defined in JEDEC document
JESD8-9. SSTL_2 maintains high-speed data bus sig-
nal integrity by reducing transmission reflections.
JEDEC further defines the DDR SDRAM specification
in JESD79C.
DDR memory requires three tightly regulated voltages:
V
DDQ
, V
TT
, and V
REF
(see
Figure 1).
In a typical
SSTL_2 receiver, the higher current V
DDQ
supply volt-
age is normally 2.5V with a tolerance of ±200-mV. The
active bus termination voltage, V
TT
, is half of V
DDQ
.
V
REF
is a reference voltage that tracks half of V
DDQ
, ±
1%, and is compared with the V
TT
terminated signal at
the receiver. V
TT
must be within ±40-mV of V
REF
.
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