CALIFORNIA MICRO DEVICES
calculating C
F
always results in a value larger than that
is required:
1
1
—————
≥
—————
2Π R
F
C
F
2Π R
S
C
S
Since the parasitic capacitance can change between
the breadboard and the production printed circuit
board, we favor the use of a “gimmick”, a technique
perfected by TV technicians in the 1950’s. A gimmick
is made by taking two lengths (typically about a foot)
of small gauge wire such as AWG 24, twisting them
together, and then after baring all ends soldering the
gimmick across R
F
. With the circuit operating, C
F
is
“adjusted” by clipping short lengths of the gimmick off
until the compensation is nominal. Then simply
remove the gimmick, take it to an impedance bridge,
and select the capacitor accordingly.
CMV1026
5. Power Supply Decoupling
The CMV1026 is not prone to oscillation without the
use of power supply decoupling capacitors, however to
minimize hum and noise pick-up, it is recommended
that the rails be bypassed with 0.01mF capacitors.
6. Turn On and Turn Off (Shut Down) Charac-
teristics
The turn off delay (Disable Response), t
OFF
, is defined
as the time between the shut down signal crossing the
disable threshold (typically V+ – 1 volt) and the time
for the amplifier’s output to come within 10% of zero. It
is largely governed by a propagation delay within the
CMV1026 of few hundred nanoseconds followed by an
exponential decay determined by the load resistance
in parallel with the load capacitance.
The turn on delay (Enable Response), t
ON
, is defined
as the time between the shutdown signal crossing the
threshold and the time the output reaches to within
10% of its final value. t
ON
is largely independent of
supply voltage and input level.
7. Typical Applications
Illustrated in Figure 4 is a Sample and Hold Amplifier
capable of operating from a single rail, but it will work
equally well with split rails The circuit will accommo-
date input voltages (common mode) from zero volts to
V+ – 1 volt. The Shut Down feature of the CMV1026 is
used to disable A
1
whose output acts like a very high
impedance in this mode. The high slew rate of the
CMV1026 and large output current minimize Acquisi-
tion Time. A
2
presents a very high input impedance
and very low bias current. A Logic “1”, a voltage
> V+ – 1 volt, will put the circuit into “Sample” mode.
A Logic “0” will put the circuit in “Hold” mode. For the
values shown, Acquisition Time to 0.1% is typically 10
µS
for a zero to 4 volt input, the hold step is typically
400
µV,
and the droop rate at 85 °C is 0.1µV/µS.
Overall accuracy is better than 0.01%. For minimum
droop, C
1
should be of polystyrene construction.
Figure 2.
4. Capacitive Load Considerations
The CMV1026 is capable of driving capacitate loads in
excess of 100pF without oscillation. However, signifi-
cant peaking will result. Probably the easiest way
minimize this problem is to use an isolation resistor as
shown in Figure 3.
Figure 3
© 2000 California Micro Devices Corp. All rights reserved.
5/00
Figure 4
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Tel: (408) 263-3214
Fax: (408) 263-7846
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11
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