CALIFORNIA MICRO DEVICES
Input Capacitance vs. Input Voltage
PAC DN007
C
IN
(pF)
V
IN
Typical variation of C
IN
with V
IN
(V
P
= 5V, V
N
= 0V, 0.1µF chip capacitor between V
P
& V
N
)
STANDARD PART ORDE RING INFORMATION
Package
Ordering Part Number
Style
Part Marking
QSOP
PACD N007Q
Pins
24
When placing an order please specify desired shipping: Tubes or Tape & Reel.
Application Information
See also California Micro Devices Application note AP209, Design Considerations for ESD protection.
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances to the Supply and Ground rails. Refer to Figure 1, which illustrates the case of a positive ESD pulse
applied between an input channel and Chassis Ground. The parasitic series inductance back to the power supply is
represented by L
1
. The voltage V
Z
on the line being protected is:
V
Z
= Forward voltage drop of D
1
+ L
1
x d(I
esd
)/dt + V
Supply
where I
esd
is the ESD current pulse, and V
Supply
is the positive supply voltage.
Figure 1
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per
the IEC 61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1nS. Here d(I
esd
)/dt can be
approximated by
∆I
esd
/∆t, or 30/(1x10
-9
). So just 10nH of series inductance (L
1
) will lead to a 300V increment in V
Z
!
© 1999 California Micro Devices Corp. All rights reserved.
2
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
11/98
CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
