PACDN009
Application Information
Design Considerations
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/
Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the
ESD protection device. Refer to
Figure 1,
which illus-
trates an example of a positive ESD pulse striking an
input channel. The parasitic series inductances back to
the power supply are represented by L
1
and L
2
. The
voltage V
CL
on the line being protected is:
V
CL
= Fwd voltage drop of D
1
+ V
SUPPLY
+ L
1
x d(I
ESD
)
/
dt
+ L
2
x d(I
ESD
)
/
dt
with R
OUT
equal to 1 ohm, we would see a 10V incre-
ment in V
CL
for a peak I
ESD
of 10A.
If the inductances and resistance described above are
close to zero, the rail-clamp ESD protection diodes will
do a good job of protection. However, since this is not
possible in practical situations, a bypass capacitor
must be used to absorb the very high frequency ESD
energy. So for any brand of rail-clamp ESD protection
diodes, a bypass capacitor should be connected
between the V
P
pin of the diodes and the ground plane
(V
N
pin of the diodes) as shown in the Application Cir-
cuit diagram below. A value of 0.22µF is adequate for
IEC-61000-4-2 level 4 contact discharge protection
(±8kV). Ceramic chip capacitors mounted with short
printed circuit board traces are good choices for this
application. Electrolytic capacitors should be avoided
as they have poor high frequency characteristics. For
extra protection, connect a zener diode in parallel with
the bypass capacitor to mitigate the effects of the para-
sitic series inductance inherent in the capacitor. The
breakdown voltage of the zener diode should be
slightly higher than the maximum supply voltage.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
to the V
P
pin of the Protection Array as possible, with
minimum PCB trace lengths to the power supply,
ground planes and between the signal input and the
ESD device to minimize stray series inductance.
where I
ESD
is the ESD current pulse, and V
SUPPLY
is
the positive supply voltage.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard
results in a current pulse that rises from zero to 30
Amps in 1ns. Here d(I
ESD
)/dt can be approximated by
∆I
ESD
/∆t, or 30/(1x10
-9
). So just 10nH of series induc-
tance (L
1
and L
2
combined) will lead to a 300V incre-
ment in V
CL
!
Similarly for negative ESD pulses, parasitic series
inductance from the V
N
pin to the ground rail will lead
to drastically increased negative voltage on the line
being protected.
Another consideration is the output impedance of the
power supply for fast transient currents. Most power
supplies exhibit a much higher output impedance to
fast transient current spikes. In the V
CL
equation
above, the V
SUPPLY
term, in reality, is given by (V
DC
+
I
ESD
x R
OUT
), where V
DC
and R
OUT
are the nominal
supply DC output voltage and effective output imped-
ance of the power supply respectively. For example,
L
2
V
P
Additional Information
See also California Micro Devices Application Notes
AP209, “Design Considerations for ESD Protection”
and AP219, "ESD Protection for USB 2.0 Systems"”
POSITIVE SUPPLY RAIL
PATH OF ESD CURRENT PULSE I
ESD
D
1
L
1
ONE
CHANNEL
OF
PAC DN009
CHANNEL
INPUT
20A
LINE BEING
PROTECTED
D
2
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
V
CL
GROUND RAIL
0A
V
N
CHASSIS GROUND
Figure 1. Application of Positive ESD Pulse between Input Channel and Ground
©
2004 California Micro Devices Corp. All rights reserved.
09/21/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
5
CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
