PACVGA105
VGA Port Companion Circuit
Features
•
7 channels of ESD protection designed to
meet IEC-1000-4-2 Level-4 ESD requirements
(8kV contact discharge)
Very low loading capacitance from ESD protection
diodes at less than 5pF typical
TTL to CMOS level-translating buffers for the
HSYNC and VSYNC lines
Three independent supply pins (V
CC
, V
RGB
and
V
AUX
) to facilitate operation with sub-micron
Graphics Controller ICs
High impedance pull-ups (50kΩ nominal to V
AUX
)
for HSYNC and VSYNC inputs
Pull-up resistors (1.8kΩ nominal to V
CC
) for
DDC_CLK and DDC_DATA lines
Compact 16-pin QSOP package
Lead-free version available
Product Description
The PACVGA105 incorporates 7 channels of ESD pro-
tection for signal lines commonly found in a VGA port
for PCs. ESD protection is implemented with current
steering diodes designed to safely handle the high
peak surge currents associated with the IEC-1000-4-2
Level-4 ESD Protection Standard (8kV contact dis-
charge). When the channels are subjected to an elec-
trostatic discharge, the ESD current pulse is diverted
via the protection diodes into the positive supply rails or
ground where they may be safely dissipated.
The upper ESD diodes for the R, G and B channels are
connected to a separate supply rail (V
RGB
) to facilitate
interfacing to graphics controller ICs with low voltage
supplies. The remaining channels are connected to the
main 5V rail (V
CC
). The lower diodes for the R, G and B
channels are also connected to a dedicated ground pin
(GNDA) to minimize crosstalk due to common ground
impedance.
Two non-inverting buffers are also included in this IC
for buffering the HSYNC and VSYNC signals from the
graphics controller IC. These buffers will accept TTL
input levels and convert them to CMOS output levels
that swing between GND and V
CC
. These drivers have
a nominal 60Ω output impedance to match the charac-
teristic impedance of the HSYNC and VSYNC lines of
the video cables typically used. The inputs of these
drivers also have high impedance pull-ups (50kΩ nom.)
pulling up to the V
AUX
rail. In addition, the
DDC_CLOCK and DDC_DATA channels have 1.8kΩ
resistors pulling these inputs up to the main 5V (V
CC
)
rail.
•
•
•
•
•
•
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Applications
•
•
•
•
ESD protection and termination resistors for VGA
(video) port interfaces
Desktop PCs
Notebook computers
LCD monitors
Simplified Electrical Schematic
V
RGB
V
CC
V
AUX
1.8k
1.8k
50k
50k
R
G
B
DDC_CLK
VSYNC_OUT
GNDD
GNDA
DDC_DATA
HSYNC
VSYNC
HSYNC_OUT
© 2004 California Micro Devices Corp. All rights reserved.
01/28/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L
Tel: 408.263.3214
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Fax: 408.263.7846
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www.calmicro.com
1
CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
