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ADCDS-1403
which is the difference between the "held" reference level
and its associated video level. When the "CDS Output" signal
has settled to the desired accuracy (user defined), the A/D
conversion process can be initiated with the rising edge of a
single start convert (Pin 25) signal.
Once the A/D conversion has been initiated, Reference Hold
(Pin 26) can be placed back into the "Acquisition" mode in
order to begin aquiring the next reference level. For optimal
performance the ADCDS-1403's internal sample-hold should
be placed back into the "Aquisition" mode (Reference Hold to
logic "0") during the CCD's "Reference Quiet Time"
("Reference Quiet Time" is defined as the period when the
CCD's reference signal has settled from all switching
transients to the desired accuracy (see Figure 10.)). Placing
the sample-hold back into the "aquisition" mode during the
"Reference Quiet Time" prevents the ADCDS-1403's internal
amplifiers from unecessarily tracking (reproducing) the large
switching transients that occur during the CCD's reset to
reference transition.
R e s e t
R e fe re n c e
" Q u ie t T im e "
C C D
O U T P U T
R e fe re n c e
V id e o
1 0 0 N S M IN .
R E F E R E N C E
H O L D
H O L D
A c q u is itio n T im e
A c q u is itio n m o d e d u r in g
R e fe r e n c e " Q u ie t T im e "
N o te : F o r o p tim a l p e r fo r m a n c e ( F a s te s t A c q u is itio n T im e ) , th e A D C D S - 1 4 0 3 s h o u ld b e p la c e d in to th e A c q u is itio n m o d e ( R e fe r e n c e H o ld to lo g ic " 0 " )
d u r in g t h e C C D o u t p u t 's R e f e r e n c e " Q u ie t T im e " . R e f e r e n c e " Q u ie t T im e " is d e f in e d a s t h e p e r io d w h e n t h e r e f e r e n c e s ig n a l's s w it c h in g t r a n s ie n t s
h a v e s e ttle d to a n a c c e p ta b le ( u s e r d e fin e d ) a c c u r a c y .
Figure 10. Reference Hold Timing
R e s e t N
R e s e t N + 1
R e s e t N + 2
R e s e t N + 3
R e s e t N + 4
C C D
O U T P U T
R e f.NN
V id e o N
R e f. N + 1
V id e o N + 1
R e f. N + 2
V V i di d e e o o N N + + 2 1
R e f. N + 3
V V i di d e e o o N N + + 3 1
R e f. N + 4
13 3 3 n s m i n .
R E F E R E N C E
H O L D IN
H o ld
1 2 0 n s m i n . s s e e t t tl i l n i n g g l i t n i m e e
A c q u is itio n
T im e
1 0 0 n s m in .
F u ll S c a le
S te p
C D S
O U T P U T
N
N + 1
1 5 0 n s mt y p i n .
N + 2
N + 3
S T A R T
C O N V E R T
N
N + 1
N + 2
N + 3
D A T A V A L ID
3 0 n s m in ., 5 0 n s m a x .
In v a lid d a ta
D A T A
O U T P U T
D A T A N -4 V A L ID
2 0 n s m ai n x
D A T A N -3 V A L ID
D A T A N -2 V A L ID
D A T A N -1 V A L ID
D A T A N V A L ID
N o t e : A s d e s c r ib e d in F ig u r e 1 0 , t h e 6 0 n s m in . is d e p e n d a n t o n t h e q u a lit y o f t h e C C D 's R e f e r e n c e w h e n t h e A D C D S - 1 4 0 3 is s w it c h e d b a c k in t o t h e t r a c k m o d e
Figure 11. ADCDS-1403 Timing Diagram
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CANDD [ C&D TECHNOLOGIES ]
