CAT24C01/02/04/08/16
ABSOLUTE MAXIMUM RATINGS
(1)
Storage Temperature
Voltage on Any Pin with Respect to Ground
(2)
RELIABILITY CHARACTERISTICS
(3)
Symbol
N
END(4)
T
DR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
-65°C to +150°C
-0.5 V to +6.5 V
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
I
CCR
I
CCW
I
SB
I
L
V
IL
V
IH
V
OL1
V
OL2
Parameter
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
V
CC
≥
2.5 V, I
OL
= 3.0 mA
V
CC
< 2.5 V, I
OL
= 1.0 mA
Test Conditions
Read, f
SCL
= 400 kHz
Write, f
SCL
= 400 kHz
All I/O Pins at GND or V
CC
Pin at GND or V
CC
-0.5
Min
Max
1
1
1
1
V
CC
x 0.3
Units
mA
mA
μA
μA
V
V
V
V
V
CC
x 0.7 V
CC
+ 0.5
0.4
0.2
PIN IMPEDANCE CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
C
IN(3)
C
IN(3)
I
WP(5)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
Conditions
V
IN
= 0 V
V
IN
= 0 V
V
IN
< V
IH,
V
CC
= 5.5 V
V
IN
< V
IH,
V
CC
= 3.3 V
V
IN
< V
IH,
V
CC
= 1.8 V
V
IN
> V
IH
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this speci-
fication is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, V
CC
= 5 V, 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull-down reverts to a weak current source.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Max
8
6
200
150
100
1
Units
pF
pF
μA
Doc. No. 1115, Rev. C
2
CATALYST [ CATALYST SEMICONDUCTOR ]
