CAT24C128
FEATURES
128-Kb I
2
C CMOS Serial EEPROM
DEVICE DESCRIPTION
The CAT24C128 is a 128-Kb Serial CMOS EEPROM,
internally organized as 16,384 words of 8 bits each.
It features a 64-byte page write buffer and supports
both the Standard (100 kHz) as well as Fast (400 kHz)
I
2
C protocol.
Write operations can be inhibited by taking the WP pin
High (this protects the entire memory).
■
Supports Standard and Fast I
2
C Protocol
■
1.8V to 5.5V Supply Voltage Range
■
64-Byte Page Write Buffer
■
Hardware Write Protection for entire memory
■
Schmitt Triggers and Noise Suppression Filters
on I
2
C Bus Inputs (SCL and SDA).
■
Low power CMOS technology
■
1,000,000 program/erase cycles
■
100 year data retention
■
Industrial and Extended temperature range
■
RoHS-compliant 8-lead PDIP, SOIC, TSSOP and
UDFN packages
PIN CONFIGURATION
PDIP (L)
SOIC (W)
TSSOP (Y)
UDFN (HU3)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
FUNCTIONAL SYMBOL
VCC
SCL
A2, A1, A0
WP
CAT24C128
SDA
For the location of Pin 1, please consult the
corresponding package drawing.
PIN FUNCTIONS
VSS
A
0
, A
1
, A
2
SDA
SCL
WP
V
CC
V
SS
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
* Catalyst carries the I
2
C protocol under a license from the Philips Corporation.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-1103, Rev. J
CATALYST [ CATALYST SEMICONDUCTOR ]
