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CAT24C164WI-GT3 参数 Datasheet PDF下载

CAT24C164WI-GT3图片预览
型号: CAT24C164WI-GT3
PDF下载: 下载PDF文件 查看货源
内容描述: 16 KB的CMOS串行EEPROM ,可级联 [16-Kb CMOS Serial EEPROM, Cascadable]
分类和应用: 内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 16 页 / 548 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT24C164  
READ OPERATIONS  
Immediate Read  
Upon receiving a Slave address with the R/W bit set to  
‘1’, the CAT24C164 will interpret this as a request for  
data residing at the current byte address in memory.  
The CAT24C164 will acknowledge the Slave address,  
will immediately shift out the data residing at the current  
address, and will then wait for the Master to respond.  
If the Master does not acknowledge the data (NoACK)  
and then follows up with a STOP condition (Figure 9),  
the CAT24C164 returns to Standby mode.  
Selective Read  
Selective Read operations allow the Master device to  
select at random any memory location for a read opera-  
tion. The Master device first performs a ‘dummy’ write  
operationbysendingtheSTARTcondition,slaveaddress  
and byte address of the location it wishes to read. After  
the CAT24C164 acknowledges the byte address, the  
Master device resends the START condition and the  
slave address, this time with the R/W bit set to one. The  
CAT24C164 then responds with its acknowledge and  
sends the requested data byte. The Master device does  
not acknowledge the data (NoACK) but will generate a  
STOP condition (Figure 10).  
Sequential Read  
If during a Read session, the Master acknowledges the  
1st data byte, then the CAT24C164 will continue trans-  
mitting data residing at subsequent locations until the  
Master responds with a NoACK, followed by a STOP  
(Figure 11). In contrast to Page Write, during Sequential  
Read the address count will automatically increment to  
and then wrap-around at end of memory (rather than  
end of page).  
© 2006 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1118, Rev. A  
8