Preliminary
CAT24WC33/65
32K/64K-Bit I
2
C Serial CMOS E
2
PROM
FEATURES
s
400 KHz I
2
C Bus Compatible*
s
1.8 to 6 Volt Read and Write Operation
s
Cascadable for up to Eight Devices
s
32-Byte Page Write Buffer
s
Self-Timed Write Cycle with Auto-Clear
s
8-Pin DIP or 8-Pin SOIC
s
Schmitt Trigger Inputs for Noise Protection
s
Zero Standby Current
s
Commercial, Industrial and Automotive Tem-
perature Ranges
s
Write Protection
–Bottom 1/4 Array Protected When WP at V
IH
s
1,000,000 Program/Erase Cycles
s
100 Year Data Retention
DESCRIPTION
The CAT24WC33/65 is a 32K/64K-bit Serial CMOS
E
2
PROM internally organized as 4096/8192 words of 8
bits each. Catalyst’s advanced CMOS technology sub-
stantially reduces device power requirements. The
CAT24WC33/65 features a 32-byte page write buffer.
The device operates via the I
2
C bus serial interface and
is available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
DIP Package (P)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
BLOCK DIAGRAM
EXTERNAL LOAD
DOUT
ACK
VCC
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
256
SENSE AMPS
SHIFT REGISTERS
SOIC Package (J,K)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
24WC33/65 F01
SDA
START/STOP
LOGIC
E
2
PROM
XDEC 128/256 128/256 X 256
WP
CONTROL
LOGIC
PIN FUNCTIONS
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
Function
Device Address Inputs
Serial Data/Address
Serial Clock
Write Protect
+1.8V to +6V Power Supply
Ground
SCL
A0
A1
A2
I
2
C
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
24WC33/65 F02
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
* Catalyst Semiconductor is licensed by Philips Corporation to carry the
Bus Protocol.
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25064-00 2/98 S-1
1
CATALYST [ CATALYST SEMICONDUCTOR ]
