CAT28C16A
16K-Bit CMOS PARALLEL E
2
PROM
FEATURES
s
Fast Read Access Times: 200 ns
s
Low Power CMOS Dissipation:
s
End of Write Detection:
DATA
Polling
s
Hardware Write Protection
s
CMOS and TTL Compatible I/O
s
10,000 Program/Erase Cycles
s
10 Year Data Retention
s
Commercial, Industrial and Automotive
–Active: 25 mA Max.
–Standby: 100
µ
A Max.
s
Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
s
Fast Write Cycle Time: 10ms Max
Temperature Ranges
DESCRIPTION
The CAT28C16A is a fast, low power, 5V-only CMOS
Parallel E
2
PROM organized as 2K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and V
CC
power up/down write protection
eliminate additional timing and protection hardware.
DATA
Polling signals the start and end of the self-timed
write cycle. Additionally, the CAT28C16A features hard-
ware write protection.
The CAT28C16A is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 10,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 24-pin DIP and SOIC or 32-pin PLCC pack-
ages.
BLOCK DIAGRAM
A4–A10
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
2,048 x 8
E
2
PROM
ARRAY
VCC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
TIMER
DATA POLLING
I/O0–I/O7
A0–A3
ADDR. BUFFER
& LATCHES
COLUMN
DECODER
5089 FHD F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25033-00 2/98