CAT28C64B
64K-Bit CMOS PARALLEL E
2
PROM
FEATURES
s
Fast Read Access Times:
s
Commercial, Industrial and Automotive
– 120/150ns
s
Low Power CMOS Dissipation:
Temperature Ranges
s
Automatic Page Write Operation:
– Active: 25 mA Max.
– Standby: 100
µA
Max.
s
Simple Write Operation:
– 1 to 32 Bytes in 5ms
– Page Load Timer
s
End of Write Detection:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
s
Fast Write Cycle Time:
– Toggle Bit
–
DATA
Polling
s
100,000 Program/Erase Cycles
s
100 Year Data Retention
– 5ms Max.
s
CMOS and TTL Compatible I/O
s
Hardware and Software Write Protection
DESCRIPTION
The CAT28C64B is a fast, low power, 5V-only CMOS
Parallel E
2
PROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and V
CC
power up/down write protection
eliminate additional timing and protection hardware.
DATA
Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C64B features hardware and software write pro-
tection.
The CAT28C64B is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC-
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC, or, 32-
pin PLCC package .
BLOCK DIAGRAM
A5–A12
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
8,192 x 8
E
2
PROM
ARRAY
32 BYTE PAGE
REGISTER
VCC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
TIMER
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
5094 FHD F02
I/O0–I/O7
A0–A4
ADDR. BUFFER
& LATCHES
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25006-0A 2/98 P-1
CATALYST [ CATALYST SEMICONDUCTOR ]
