CAT28C64B
Byte Write
DEVICE OPERATION
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Read
Data stored in the CAT28C64B is transferred to the data
bus when WE is held high, and both OE and CE are held
low. The data bus is set to a high impedance state when
either CE or OE goes high. This 2-line control architec-
ture can be used to eliminate bus contention in a system
environment.
Figure 3. Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
V
IH
t
WE
LZ
t
OHZ
t
t
HZ
DATA VALID
t
OH
OLZ
HIGH-Z
DATA OUT
DATA VALID
t
AA
Figure 4. Byte Write Cycle [WE Controlled]
t
WC
ADDRESS
t
t
AH
AS
t
t
CH
CS
CE
OE
WE
t
t
t
OEH
OES
WP
t
BLC
HIGH-Z
DATA OUT
DATA IN
DATA VALID
DS
t
t
DH
Doc. No. 1011, Rev. F
7
CATALYST [ CATALYST SEMICONDUCTOR ]
