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CAT28F001G-12BT 参数 Datasheet PDF下载

CAT28F001G-12BT图片预览
型号: CAT28F001G-12BT
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位的CMOS引导块闪存 [1 Megabit CMOS Boot Block Flash Memory]
分类和应用: 闪存存储内存集成电路
文件页数/大小: 18 页 / 456 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT28F001
1 Megabit CMOS Boot Block Flash Memory
FEATURES
I
Fast Read Access Time: 90/120 ns
I
On-Chip Address and Data Latches
I
Blocked Architecture
Licensed Intel
second source
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
I
Deep Powerdown Mode
I
I
I
I
I
— One 8 KB Boot Block w/ Lock Out
• Top or Bottom Locations
— Two 4 KB Parameter Blocks
— One 112 KB Main Block
Low Power CMOS Operation
12.0V
±
5% Programming and Erase Voltage
Automated Program & Erase Algorithms
High Speed Programming
Commercial, Industrial and Automotive
Temperature Ranges
I
I
I
I
I
I
— 0.05
µ
A I
CC
Typical
— 0.8
µ
A I
PP
Typical
Hardware Data Protection
Electronic Signature
100,000 Program/Erase Cycles and 10 Year
Data Retention
JEDEC Standard Pinouts:
— 32 pin DIP
— 32 pin PLCC
— 32 pin TSOP
Reset/Deep Power Down Mode
"Green" Package Options Available
DESCRIPTION
The CAT28F001 is a high speed 128K X 8 bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after sale
code updates.
The CAT28F001 has a blocked architecture with one 8
KB Boot Block, two 4 KB Parameter Blocks and one 112
KB Main Block. The Boot Block section can be at the top
or bottom of the memory map and includes a reprogram-
ming write lock out feature to guarantee data integrity. It
is designed to contain secure code which will bring up
the system minimally and download code to other loca-
tions of CAT28F001.
The CAT28F001 is designed with a signature mode
which allows the user to identify the IC manufacturer and
device type. The CAT28F001 is also designed with on-
Chip Address Latches, Data Latches, Programming and
Erase Algorithms.
The CAT28F001 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, PLCC or TSOP packages.
BLOCK DIAGRAM
I/O0–I/O7
ADDRESS
COUNTER
I/O BUFFERS
WRITE STATE
MACHINE
RP
WE
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
DATA
LATCH
SENSE
AMP
ERASE VOLTAGE
SWITCH
STATUS
REGISTER
CE
OE
ADDRESS LATCH
Y-GATING
Y-DECODER
8K-BYTE BOOT BLOCK
4K-BYTE PARAMETER BLOCK
4K-BYTE PARAMETER BLOCK
112K-BYTE MAIN BLOCK
A0–A16
VOLTAGE VERIFY
SWITCH
X-DECODER
COMPARATOR
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1078, Rev. I