欢迎访问ic37.com |
会员登录 免费注册
发布采购

CAT28F020N-12T 参数 Datasheet PDF下载

CAT28F020N-12T图片预览
型号: CAT28F020N-12T
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位的CMOS闪存 [2 Megabit CMOS Flash Memory]
分类和应用: 闪存存储内存集成电路
文件页数/大小: 15 页 / 431 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
 浏览型号CAT28F020N-12T的Datasheet PDF文件第2页浏览型号CAT28F020N-12T的Datasheet PDF文件第3页浏览型号CAT28F020N-12T的Datasheet PDF文件第4页浏览型号CAT28F020N-12T的Datasheet PDF文件第5页浏览型号CAT28F020N-12T的Datasheet PDF文件第6页浏览型号CAT28F020N-12T的Datasheet PDF文件第7页浏览型号CAT28F020N-12T的Datasheet PDF文件第8页浏览型号CAT28F020N-12T的Datasheet PDF文件第9页  
CAT28F020
2 Megabit CMOS Flash Memory
Licensed Intel second source
FEATURES
I
Fast read access time: 90/120 ns
I
Low power CMOS dissipation:
H
GEN
FR
ALO
EE
LE
I
Commercial, industrial and automotive
A
D
F
R
E
E
TM
temperature ranges
I
Stop timer for program/erase
I
On-chip address and data latches
I
JEDEC standard pinouts:
– Active: 30 mA max (CMOS/TTL levels)
– Standby: 1 mA max (TTL levels)
– Standby: 100
µ
A max (CMOS levels)
I
High speed programming:
– 10
µ
s per byte
– 4 seconds typical chip program
– 32-pin DIP
– 32-pin PLCC
– 32-pin TSOP (8 x 20)
I
100,000 program/erase cycles
I
10 year data retention
I
Electronic signature
I
0.5 seconds typical chip-erase
I
12.0V
±
5% programming and erase voltage
DESCRIPTION
The CAT28F020 is a high speed 256K x 8-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and E
2
PROM devices. Programming and
Erase are performed through an operation and verify
algorithm. The instructions are input via the I/O bus,
using a two write cycle scheme. Address and Data are
latched to free the I/O bus and address bus during the
write operation.
The CAT28F020 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
TSOP packages.
BLOCK DIAGRAM
I/O0–I/O7
I/O BUFFERS
ERASE VOLTAGE
SWITCH
WE
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
DATA
LATCH
SENSE
AMP
CE
OE
ADDRESS LATCH
Y-GATING
Y-DECODER
2,097,152 BIT
MEMORY
ARRAY
5115 FHD F02
A0–A17
X-DECODER
VOLTAGE VERIFY
SWITCH
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1029, Rev. C