CAT28F020
2 Megabit CMOS Flash Memory
FEATURES
s
Fast Read Access Time: 70/90/120 ns
s
Low Power CMOS Dissipation:
Licensed Intel
second source
s
Commercial, Industrial and Automotive
Temperature Ranges
s
Stop Timer for Program/Erase
s
On-Chip Address and Data Latches
s
JEDEC Standard Pinouts:
– Active: 30 mA max (CMOS/TTL levels)
– Standby: 1 mA max (TTL levels)
– Standby: 100
µ
A max (CMOS levels)
s
High Speed Programming:
– 10
µ
s per byte
– 4 Seconds Typical Chip Program
– 32-pin DIP
– 32-pin PLCC
– 32-pin TSOP (8 x 20)
s
100,000 Program/Erase Cycles
s
10 Year Data Retention
s
Electronic Signature
s
0.5 Seconds Typical Chip-Erase
s
12.0V
±
5% Programming and Erase Voltage
DESCRIPTION
The CAT28F020 is a high speed 256K x 8-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and E
2
PROM devices. Programming and
Erase are performed through an operation and verify
algorithm. The instructions are input via the I/O bus,
using a two write cycle scheme. Address and Data are
latched to free the I/O bus and address bus during the
write operation.
The CAT28F020 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
TSOP packages.
BLOCK DIAGRAM
I/O0–I/O7
I/O BUFFERS
ERASE VOLTAGE
SWITCH
WE
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
DATA
LATCH
SENSE
AMP
CE
OE
ADDRESS LATCH
Y-GATING
Y-DECODER
2,097,152 BIT
MEMORY
ARRAY
5115 FHD F02
A0–A17
X-DECODER
VOLTAGE VERIFY
SWITCH
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25037-00 2/98 F-1