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CAT5241YI-10 参数 Datasheet PDF下载

CAT5241YI-10图片预览
型号: CAT5241YI-10
PDF下载: 下载PDF文件 查看货源
内容描述: 四路数字可编程电位计( DPP⑩ )与64丝锥和2线接口 [Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and 2-wire Interface]
分类和应用: 转换器数字电位计电阻器光电二极管
文件页数/大小: 16 页 / 113 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT5241
Quad Digitally Programmable Potentiometers (DPP™)
with 64 Taps and 2-wire Interface
FEATURES
s
Four linear-taper digitally programmable
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
s
Automatic recall of saved wiper settings at
potentiometers
s
64 resistor taps per potentiometer
s
End to end resistance 2.5k
, 10k
, 50k
or 100k
s
Potentiometer control and memory access via
power up
s
2.5 to 6.0 volt operation
s
Standby current less than 1
µ
A
s
1,000,000 nonvolatile WRITE cycles
s
100 year nonvolatile memory data retention
s
20-lead SOIC and TSSOP packages
s
Industrial temperature range
2-wire interface (I
2
C like)
s
Low wiper resistance, typically 80Ω
s
Nonvolatile memory storage for up to four wiper
settings for each potentiometer
DESCRIPTION
The CAT5241 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of 63 resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper outputs
with CMOS switches. A separate 6-bit control register
(WCR) independently controls the wiper tap switches for
each DPP. Associated with each wiper control register
are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
wiper control register or any of the non-volatile data
registers is via a 2-wire serial bus (I
2
C-like). On power-
up, the contents of the first data register (DR0) for each
of the four potentiometers is automatically loaded into its
respective wiper control register (WCR).
The CAT5241 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC Package (J, W)
TSSOP Package (U, Y)
RW0
RL0
RH0
A0
A2
RW1
RL1
RH1
SDA
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
CAT
16
5241
15
14
13
12
11
VCC
RW3
RL3
RH3
A1
A3
SCL
RW2
RL2
RH2
FUNCTIONAL DIAGRAM
RH0 RH1
RH2 R H3
SCL
SDA
2-WIRE BUS
INTERFACE
WIPER
CONTROL
REGISTERS
R W0
R W1
R W2
A0
A1
A2
A3
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R W3
RL0 RL1
RL2 R L3
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Document No. 2011, Rev. J