CAT5259
Quad Digitally Programmable Potentiometers
(DPP™) with 256 Taps and I²C Interface
FEATURES
Four linear taper digitally programmable
potentiometers
256 resistor taps per potentiometer
End to end resistance 50kΩ or 100kΩ
Potentiometer control and memory access via
I²C interface
Low wiper resistance, typically 100Ω
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP packages
Industrial temperature range
DESCRIPTION
The CAT5259 is four digitally programmable poten–
tiometers (DPPs™) integrated with control logic and
16 bytes of NVRAM memory. Each DPP consists of a
series of resistive elements connected between two
externally accessible end points. The tap points
between each resistive element are connected to the
wiper outputs with CMOS switches. A separate 8-bit
control register (WCR) independently controls the
wiper tap switches for each DPP. Associated with
each wiper control register are four 8-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a I²C serial
bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers
is automatically loaded into its respective wiper
control registers.
The CAT5259 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the 0ºC to 70ºC
commercial and -40ºC to 85ºC industrial operating
temperature ranges and offered in a 24-lead SOIC
and TSSOP package.
PIN CONFIGURATION
SOIC (W)
TSSOP (Y)
NC
A0
R
W3
R
H3
R
L3
NC
V
CC
R
LO
R
HO
1
2
3
4
5
6
7
8
9
24 A3
23 SCL
22 R
L2
21 R
H2
20 R
W2
19 NC
18 GND
17 R
W1
16 R
H1
15 R
L1
14 A1
13 SDA
WP
A
0
A
1
A
2
A
3
SCL
SDA
FUNCTIONAL DIAGRAM
R
H0
R
H1
R
H2
R
H3
I²C BUS
INTERFACE
WIPER CONTROL
REGISTERS
R
W0
R
W1
CONTROL LOGIC
NONVOLATILE
DATA
REGISTERS
R
W2
R
W3
R
L0
R
L1
R
L2
R
L3
R
WO
10
A2 11
¯¯¯ 12
WP
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-2000 Rev. H
CATALYST [ CATALYST SEMICONDUCTOR ]
