CAT5259
SERIAL BUS PROTOCOL
The following defines the features of the I²C bus
protocol:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high will
be interpreted as a START or STOP condition.
The device controlling the transfer is a master,
typically a processor or controller, and the device
being controlled is the slave. The master will always
initiate data transfers and provide the clock for both
transmit and receive operations. Therefore, the
CAT5259 will be considered a slave device in all
applications.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT5259 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
The CAT5259 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each 8-bit byte.
When the CAT5259 is in a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the line
for an acknowledge. Once it receives this acknowledge,
the CAT5259 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
WRITE OPERATIONS
In the Write mode, the Master device sends the
START condition and the slave address information to
the Slave device. After the Slave generates an
acknowledge, the Master sends the instruction byte
that defines the requested operation of CAT5259. The
instruction byte consist of a four-bit opcode followed
by two register selection bits and two pot selection
bits. After receiving another acknowledge from the
Slave, the Master device transmits the data to be
written into the selected register. The CAT5259
acknowledges once more and the Master generates
the STOP condition, at which time if a non-volatile
data register is being selected, the device begins an
internal programming cycle to non-volatile memory.
While this internal cycle is in progress, the device will
not respond to any request from the Master device.
Acknowledge Polling
The disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host's write operation, the CAT5259 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address. If the CAT5259 is still
busy with the write operation, no ACK will be returned.
If the CAT5259 has completed the write operation, an
ACK will be returned and the host can then proceed
with the next instruction operation.
Write Protection
The Write Protection feature allows the user to protect
against inadvertent programming of the non-volatile data
registers. If the ¯¯¯ pin is tied to LOW, the data registers
WP
are protected and become read only. Similarly, the ¯¯¯
WP
pin is going low after start will interrupt non-volatile write
to data registers, while ¯¯¯ pin going low after an
WP
internal write cycle has started will have no effect on any
write operation. The CAT5259 will accept both slave
addresses and instructions, but the data registers are
protected from programming by the device’s failure to
send an acknowledge after data is received.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
fixed as 0101 for the CAT5259 (see Figure 5). The
next four significant bits (A3, A2, A1, A0) are the
device address bits and define which device the
Master is accessing. Up to sixteen devices may be
individually addressed by the system. Typically, +5V
and ground are hard-wired to these pins to establish
the device's address.
After the Master sends a START condition and the
slave address byte, the CAT5259 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address.
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8
bits of data.
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Doc. No. MD-2000 Rev. H
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CATALYST [ CATALYST SEMICONDUCTOR ]
