CAT5401
Quad Digitally Programmable Potentiometers
(DPP™) with 64 Taps and SPI Interface
FEATURES
Four linear taper digitally programmable
potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5kΩ, 10kΩ, 50kΩ or
100kΩ
Potentiometer control and memory access via
SPI interface: Mode (0, 0) and (1, 1)
Low wiper resistance, typically 80Ω
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP
Industrial temperature range
DESCRIPTION
The CAT5401 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists
of a series of 63 resistive elements connected
between two externally accessible end points. The tap
points between each resistive element are connected
to the wiper outputs with CMOS switches. A separate
6-bit control register (WCR) independently controls
the wiper tap switches for each DPP. Associated with
each wiper control register are four 6-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a SPI serial
bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers is
automatically loaded into its respective wiper control
register.
The CAT5401 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC Package (W)
VCC
RL0
RH0
RW0
CS
WP
SI
A1
RL1
RH1
RW1
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
CAT
19
5401
18
17
16
15
14
13
NC
RL3
RH3
RW3
A0
SO
HOLD
SCK
RL2
RH2
SI
A1
RL1
RH1
RW1
GND
NC
RW2
RH2
RL2
TSSOP Package (Y)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
CAT
19
5401
18
17
16
15
14
13
WP
CS
RW0
RH0
RL0
VCC
NC
RL3
RH3
RW3
A0
SO
FUNCTIONAL DIAGRAM
R
H0
CS
SCK
SI
SO
R
H1
R
H2
R
H3
SPI BUS
INTERFACE
WIPER CONTROL
REGISTERS
R
W0
R
W1
WP
A
0
A
1
CONTROL LOGIC
NONVOLATILE
DATA
REGISTERS
R
W2
R
W3
RW2
SCK
NC
HOLD
R
L0
R
L1
R
L2
R
L3
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-2012 Rev. G
CATALYST [ CATALYST SEMICONDUCTOR ]
