CAT64LC10/20/40
1K/2K/4K-Bit SPI Serial EEPROM
FEATURES
s
SPI bus compatible
s
Low power CMOS technology
s
2.5V to 6.0V operation
s
Self-timed write cycle with auto-clear
s
Hardware reset pin
s
Hardware and software write protection
H
LOGEN
FR
A
EE
LE
A
D
F
R
E
E
TM
s
Commercial, industrial and automotive
temperature ranges
s
Power-up inadvertant write protection
s
RDY/BSY pin for end-of-write indication
BSY
s
1,000,000 program/erase cycles
s
100 year data retention
DESCRIPTION
The CAT64LC10/20/40 is a 1K/2K/4K-bit Serial EEPROM
which is configured as 64/128/256 registers by 16 bits.
Each register can be written (or read) serially by using
the DI (or DO) pin. The CAT64LC10/20/40 is
manufactured using Catalyst’s advanced CMOS
EEPROM floating gate technology. It is designed to
endure 1,000,000 program/erase cycles and has a data
retention of 100 years. The device is available in 8-pin
DIP, SOIC and TSSOP packages.
PIN CONFIGURATION
DIP Package (P, L)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
RDY/BUSY
RESET
GND
SOIC Package (J, W)
RDY/BUSY
VCC
CS
SK
1
2
3
4
8
7
6
5
RESET
GND
DO
DI
TSSOP Package (U, Y)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
RDY/BUSY
RESET
GND
SOIC Package (S, V)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
RDY/BUSY
RESET
GND
TSSOP Package (UR, YR)
RDY/BUSY
VCC
CS
SK
1
2
3
4
8
7
6
5
RESET
GND
DO
DI
PIN FUNCTIONS
Pin Name
CS
SK
DI
DO
V
CC
GND
RESET
RDY/BUSY
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
+2.5V to +6.0V Power Supply
Ground
Reset
Ready/BUSY Status
BLOCK DIAGRAM
VCC
GND
MEMORY ARRAY
64/128/256 x 16
ADDRESS
DECODER
DATA
REGISTER
DI
RESET
CS
MODE DECODE
LOGIC
OUTPUT
BUFFER
SK
CLOCK
GENERATOR
DO
RDY/BUSY
64LC10/20/40 F02
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1021, Rev. B
CATALYST [ CATALYST SEMICONDUCTOR ]
