ULTRA LOW NOISE
PSEUDOMORPHIC HJ FET
FEATURES
• SUPER LOW NOISE FIGURE:
0.35 dB Typ at f = 12 GHz
Noise Figure, NF (dB)
NE321000
NOISE FIGURE & ASSOCIATED GAIN vs.
DRAIN CURRENT
V
DS
= 2 V
f = 12 GHz
15
G
A
14
13
2.0
1.5
1.0
0.5
NF
0
10
20
30
12
11
• GATE LENGTH:
≤0.2
µm
• GATE WIDTH:
160
µm
DESCRIPTION
NEC's NE321000 is a Hetero-Junction FET chip that utilizes
the junction between Si-doped AlGaAs and undoped InGaAs
to create high electron mobility. Its excellent low noise figure
and high associated gain make it suitable for commercial,
industrial and space applications.
NEC's stringent quality assurance and test procedures assure
the highest reliability and performance.
Drain Current, I
D
(mA)
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C)
PART NUMBER
PACKAGE OUTLINE
SYMBOLS
NF
G
A1
I
DSS
V
P
g
M
I
GSO
PARAMETERS AND CONDITIONS
Noise Figure, V
DS
= 2 V, I
D
= 10 mA, f = 12 GHz
Associated Gain, V
DS
= 2 V, I
D
= 10 mA, f = 12 GHz
Saturated Drain Current, V
DS
= 2 V, V
GS
= 0 V
Pinch-off Voltage, V
DS
= 2 V, I
D
= 100
µA
Transconductance, V
DS
= 2 V, I
D
= 10
µA
Gate to Source Leakage Current, V
GS
= -3 V
UNITS
dB
dB
mA
V
mS
µA
12.0
15
-0.2
40
MIN
NE321000
CHIP
TYP
0.35
13.5
40
-0.7
55
0.5
10
70
-2.0
MAX
0.45
Note:
1. RF performance is determined by packaging and testing 10 samples per wafer. Wafer rejection criteria for standard devices is 2 rejects per
10 samples.
California Eastern Laboratories
Associated Gain, G
A
(dB)
• HIGH ASSOCIATED GAIN:
13.0 dB Typ at f = 12 GHz
CEL [ CALIFORNIA EASTERN LABS ]
