UPC2745TB, UPC2746TB
ELECTRICAL CHARACTERISTICS
(T
A
= +25
°C,
Z
L
= Z
S
= 50
Ω)
SYMBOLS
RL
IN
PART NUMBER
PACKAGE OUTLINE
PARAMETERS AND CONDITIONS
Input Return Loss, V
CC
= 3.0 V, f = 0.5 GHz
V
CC
= 3.0 V, f = 1 GHz
V
CC
= 3.0 V, f = 2 GHz
V
CC
= 1.8 V, f = 0.5 GHz
Output Return Loss, V
CC
= 3.0 V, f = 0.5 GHz
V
CC
= 3.0 V, f = 1 GHz
V
CC
= 3.0 V, f = 2 GHz
V
CC
= 1.8 V, f = 0.5 GHz
Isolation, V
CC
= 3.0 V, f = 0.5 GHz
V
CC
= 3.0 V, f = 1 GHz
V
CC
= 3.0 V, f = 2 GHz
V
CC
= 1.8 V, f = 0.5 GHz
3rd Order Intermodulation Distortion
V
CC
= 3.0 V, P
OUT
= -20 dBm, f1 = 500 MHz, f2 = 502 MHz
V
CC
= 3.0 V, P
OUT
= -20 dBm, f1 = 1000 MHz, f2 = 1002 MHz
V
CC
= 1.8 V, P
OUT
= -20 dBm, f1 = 500 MHz, f2 = 502 MHz
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBc
dBc
dBc
UPC2745TB
S06
MIN
TYP
MAX
8
11
13
14
6.5
5.5
6.5
8.5
6.0
38
33
30
35
-54
-50
-31
UPC2746TB
S06
MIN
TYP
MAX
10
13
10
10
8.5
8.5
9.5
45
38
37
-51
-37
RL
OUT
2.5
5.5
ISOL
33
40
IM3
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C)
SYMBOLS
V
CC
P
IN
P
T
T
OP
T
STG
PARAMETERS
Supply Voltage (Pin 5, Pin 8)
Input Power
Total Power Dissipation
2
Operating Temperature
Storage Temperature
UNITS
V
dBm
mW
°C
°C
RATINGS
4.0
0
200
-45 to +85
-55 to +150
RECOMMENDED
OPERATING CONDITIONS
SYMBOL
V
CC
T
OP
PARAMETER
Supply Voltage
Operating Temperature
UNITS
V
˚C
MIN
2.7
-40
TYP MAX
3.0
+25
3.3
+85
Notes:
1. Operation in excess of any one of these parameters may result
in permanent damage.
2. Mounted on double sided copper clad 50 x 50 x 1.6 mm epoxy
glass PWB (T
A
= +85°C).
PIN DESCRIPTION
Pin
No.
Pin
Name
Applied
Voltage
(V)
Description
Internal Equivalent Circuit
1
Input
Signal input pin. An internal matching
circuit, configured with resistors, enables
50
Ω
connection over a wide bandwidth.
This pin must be coupled to the signal source
with a blocking capacitor.
6
4
4
Output
Signal output pin. An internal matching
circuit, configured with resistors, enables
50
Ω
connection over a wide bandwidth.
This pin must be coupled to the output
load with a blocking capacitor.
2.7 to 3.3
Power supply pin. This pin should be
externally equipped with a bypass capacitor
to minimize ground impedance.
Ground pin. This pin should be connected
to system ground with minimum inductance.
Ground pattern on the board should be
formed as wide as possible. All the ground
pins must be connected together with wide
ground pattern to minimize impedance
difference.
1
6
V
CC
2
3
5
GND
0
2
3
5
CEL [ CALIFORNIA EASTERN LABS ]
