CTM8B54E/55E/56E/57E
EPROM-Based 8-Bit CMOS Microcontroller
Mnemonic
Operands
DECR R, d
Description
Decrement R
Cycles
1
1 or
2(skip)
1
1
1
1
1
Instruction
Code
Status
Affected
01 0110 drrr rrrr
Z
01 0111 drrr rrrr
None
01 1010 drrr rrrr
C, DC, Z
01 1011 drrr rrrr
Z
01 0100 drrr rrrr
Z
01 0101 drrr rrrr
C, DC, Z
01 1111 drrr rrrr
Z
DECRSZ R, d Decrement R, Skip if 0
SUBAR R, d
XORAR R, d
ANDAR R, d
ADDAR R, d
IORAR R, d
Note:
Subtract Acc from R
Exclusive OR Acc with R
AND Acc with R
Add Acc and R
Inclusive OR Acc with R
b : Bit position
WDT : Watchdog Timer
R : Register address
i : Immediate data
Acc : Accumulator
T0MODE : T0MODE register
PD : Power down flag
TO : Time overflow bit
IOST : I/O port status register
Z : Zero flag
C : Carry flag
DC : Digital carry flag
I : (i
7
i
6
i
5
i
4
i
3
i
2
i
1
i
0
)
R : (r
6
r
5
r
4
r
3
r
2
r
1
r
0
)
d
∈ [
0
,
1
]
:Destination
If d is “0”, the result is stored in the Acc register.
If d is “1”, the result is stored back in register R.
3.3 I/O PORTS EQUIVALENT CIRCUIT
Acc Data
D
Q
VDD
IOST
Latch
IOST R
CK
QB
I/O Pin
Data Bus
D
QB
Data
Latch
WR Port
CK
Q
VSS
RD Port
Note : 1. The IOST registers are “write-only” and set upon RESET.
2. If the IOST latch is “0”, the corresponding I/O pin is in output mode;
if the IOST latch is “1”, the corresponding I/O pin is in input mode.
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Email: server@ceramate.com.tw
Tel:886-3-3529445
Http: www.ceramate.com.tw
Page 8 of
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Rev 1.1 Dec 26,2001
Fax:886-3-3521052
CERAMATE [ CERAMATE TECHNICAL ]
