CEF10N4
Sep. 2002
N-Channel Logic Level Enhancement Mode Field Effect Transistor
FEATURES
450V ,5.6A ,R
DS(ON)
= 700m
Ω
@V
GS
=10V.
Super high dense cell design for extremely low R
DS(ON)
.
High power and current handling capability.
TO-220F full-pak for through hole.
D
6
G
G
D
S
TO-220F
S
ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
-Pulsed
Drain-Source Diode Forward Current
Maximum Power Dissipation
@Tc=25 C
Derate above 25 C
Operating and Storage Temperature Range
Symbol
V
DS
V
GS
I
D
I
DM
I
S
P
D
T
J
, T
STG
Limit
450
30
5.6
17
5.6
45
0.36
-55 to 150
Unit
V
V
A
A
A
W
W/ C
C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
R
JC
R
JA
6-107
2.8
65
C/W
C
/W
CET [ CHINO-EXCEL TECHNOLOGY ]
