CED41A2/CEU41A2
V
GS
, Gate to Source Voltage (V)
5
V
DS
=10V
I
D
=10.7A
10
3
I
D
, Drain Current (A)
4
10
2
R
DS(ON)
Limit
100µs
1ms
10ms
3
2
10
1
DC
1
0
0
4
8
12
16
10
0
T
C
=25 C
T
J
=175 C
Single Pulse
10
-1
6
10
0
10
1
10
2
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
V
DS
, Drain-Source Voltage (V)
Figure 8. Maximum Safe
Operating Area
V
DD
t
on
V
IN
D
V
GS
R
GEN
G
90%
t
off
t
r
90%
R
L
V
OUT
t
d(on)
V
OUT
t
d(off)
90%
10%
t
f
10%
INVERTED
S
V
IN
50%
10%
50%
PULSE WIDTH
Figure 9. Switching Test Circuit
Figure 10. Switching Waveforms
r(t),Normalized Effective
Transient Thermal Impedance
10
0
D=0.5
0.2
10
-1
0.1
0.05
0.02
0.01
Single Pulse
P
DM
t
1
t
2
1. R
θJC
(t)=r (t) * R
θJC
2. R
θJC
=See Datasheet
3. T
JM-
T
C
= P* R
θJC
(t)
4. Duty Cycle, D=t1/t2
10
-2
10
-2
10
-1
10
0
10
1
10
2
10
3
10
4
Square Wave Pulse Duration (msec)
Figure 11. Normalized Thermal Transient Impedance Curve
6 - 65
CET [ CHINO-EXCEL TECHNOLOGY ]
