CM6805(A;B)/CM6806A
10-PIN Green-Mode PFC/PWM Combo CONTROLLER for High Density AC Adapter
The ISENSE Filter is a RC filter. The resistor value of the
PWM section wakes up after PFC reaches steady state
PWM section is off all the time before PFC VFB reaches
2.45V. Then internal 10mS digital PWM soft start circuit
slowly ramps up the soft-start voltage.
ISENSE Filter is between 100 ohm and 50 ohm. By selecting
RFILTER equal to 50 ohm will keep the offset of the IEAO less
than 5mV. Usually, we design the pole of ISENSE Filter at
fpfc/6, one sixth of the PFC switching frequency. Therefore,
the boost inductor can be reduced 6 times without
disturbing the stability. Therefore, the capacitor of the ISENSE
Filter, CFILTER, will be around 283nF.
PFC OVP Comparator
PFC OVP Comparator sense VFB pin which is the same the
voltage loop input. The good thing is the compensation
network is connected to VEAO. The PFC OVP function is a
relative fast OVP. It is not like the conventional error amplifier
which is an operational amplifier and it requires a local
feedback and it make the OVP action becomes very slow.
The threshold of the PFC OVP is 2.5V+10% =2.75V with
250mV hysteresis.
IAC, RAC, Automatic Slope Compensation, DCM at high line
and light load, and Startup current
There are 4 purposes for IAC pin:
1.) For the leading edge modulation, when the duty
cycle is less than 50%, it requires the similar slope
compensation, as the duty cycle of the trailing
edge modulation is greater than 50%. In the
CM6805A/CM6806A, it is a relatively easy thing to
design. Use an more than 800K ohm resistor, RAC
to connect IAC pin and the rectified line voltage. It
will do the automatic slope compensation. If the
input boost inductor is too small, the RAC may
need to be reduced more.
PFC Tri-Fault Detect Comparator
To improve power supply reliability, reduce system
component count, and simplify compliance to UL1950 safety
standards, the CM6805A/CM6806A includes PFC Tri-Fault
Detect. This feature monitors VFB (Pin 5) for certain PFC
fault conditions.
2.) During the startup period, Rac also provides the
initial startup current, 100uA;therefore, the bleed
resistor is not needed.
3.) Since IAC pin with RAC behaves as a feedforward
signal, it also enhances the signal to noise ratio
and the THD of the input current.
In case of a feedback path failure, the output of the PFC
could go out of safe operating limits. With such a failure, VFB
will go outside of its normal operating area. Should VFB go
too low, too high, or open, PFC Tri-Fault Detect senses the
error and terminates the PFC output drive.
4.) It also will try to keep the maximum input power to
be constant. However, the maximum input power
will still go up when the input line voltage goes up.
PFC Tri-Fault detect is an entirely internal circuit. It requires
no external components to serve its protective function.
VCC OVP and generate VCC
Start Up of the system, UVLO, VREFOK and Soft Start
During the Start-up period, RAC resistor will provide the start
up current~100uA from the rectified line voltage to IAC pin.
Inside of CM6805A/CM6806A during the start-up period,
IAC is connected to VCC until the VCC reaches UVLO
voltage which is 15V and internal reference voltage is
stable, it will disconnect itself from VCC. During the Start
up, the soft start function is triggered and the duration of the
soft start will last around 10mS.
For the CM6805A/CM6806A system, if VCC is generated
from a source that is proportional to the PFC output voltage
and once that source reaches 17.9V, PFCOUT, PFC driver
will be off.
The VCC OVP resets once the VCC discharges below
16.4V, PFC output driver is enabled. It serves as redundant
PFC OVP function.
Typically, there is a bootstrap winding off the boost inductor.
The VCC OVP comparator senses when this voltage
exceeds 17.9V, and terminates the PFC output drive. Once
the VCC rail has decreased to below 16.4V the PFC output
drive be enabled. Given that 16V on VCC corresponds to
380V on the PFC output, 17.9V on VCC corresponds to an
OVP level of 460V.
PFC section wakes up after Start up period
After Start up period, PFC section will softly start since
VEAO is zero before the start-up period. Since VEAO is a
slew rate enhanced transconductance amplifier (see figure
3), VEAO has a high impedance output like a current
source and it will slowly charge the compensation net work
which needs to be designed by using the voltage loop gain
equation.
It is a necessary to put RC filter between bootstrap winding
and VCC. For VCC=15V, it is sufficient to drive either a
power MOSFET or a IGBT.
Before PFC boost output reaches its design voltage, it is
around 380V and VFB reaches 2.5V, PWM section is off.
2006/10/11 Rev1.0
Champion Microelectronic Corporation
Page 11
CHAMP [ CHAMPION MICROELECTRONIC CORP. ]
