CS51021/22/23/24
Package Pin Description: continued
PACKAGE PIN #
PIN SYMBOL
FUNCTION
16L PDIP & SO Narrow
7
8
R
T
C
T
I
SET
Timing resistor R
T
and capacitor C
T
determine oscillator frequen-
cy and maximum duty cycle, D
MAX
.
Voltage at this pin sets pulse-by-pulse overcurrent threshold, and
second threshold (1.33 times higher) with Soft Start retrigger (hic-
cup mode).
Feedback voltage input. Connected to the error amplifier invert-
ing input.
Error amplifier output. Frequency compensation network is usu-
ally connected between COMP and V
FB
pins.
Charging external capacitor restricts error amplifier output volt-
age during the start or fault conditions (hiccup).
Logic ground.
5.0V reference voltage output.
Logic supply voltage.
Output power stage ground connection.
Output power stage supply voltage.
Block Diagram
V
CC
-
+
START
STOP
Vcc_OK
9
10
11
12
13
14
15
16
V
FB
COMP
SS
LGnd
V
REF
V
CC
PGnd
V
C
V
REF
VREF = 5V
V
REF
_OK
+
LGnd
SLEEP
SYNC
R
T
C
T
V
C
200ns
4.3V
OSC
4.75V
G2
D4
ZD1
13.5V
S
F1
SS
Clamp
D2
G1
I
SET
Clamp
D3
+
2.5V
-
E/A
D1
V
REF
53µA
+
–
2V
V
FB
Monitor
G4
DISABLE
0.1V
+
–
SS
Monitor
+
Q
GATE
R
COMP
PGnd
20k
10k
PWM
Comp
V
REF
55µA
V
FB
SS
SLOPE
I
SENSE
Q2
×
×
0.1
0.8
∑
55ns
Blank
V
ISense
4.7V
–
1.33
2nd
Threshold
I
SET
OV
V
REF
12.5µA
×
G3
FAULT
Discharge
Latch
OV
Monitor
+
2.5V
–
UV
Monitor
+
UV
1.45V
–
Figure 1: CS51021/22/23/24 Block Diagram
5
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
