CS51221
Package Pin Description
Typical Performance Characteristics
PACKAGE PIN #
PIN SYMBOL
FUNCTION
16L PDIP & 16L SO Narrow
1
GATE
External power switch driver with 1.0A peak capability. Rail to
rail output occurs when the capacitive load is between 470pF
and 10nF.
Current sense comparator input.
Bidirectional synchronization. Locks to highest frequency.
PWM ramp.
Undervoltage protection monitor.
Overvoltage protection monitor.
Timing resistor R
T
and capacitor C
T
determine oscillator
frequency and maximum duty cycle, D
MAX
.
Voltage at this pin sets pulse-by-pulse overcurrent threshold.
Feedback voltage input. Connected to the error amplifier
inverting input.
Error amplifier output.
Charging external capacitor restricts error amplifier output
voltage during the power up or fault conditions.
Logic Ground.
3.3V reference voltage output. Decoupling capacitor can be
selected from 0.01µF to 10µF.
Logic supply voltage.
Output power stage ground.
Output power stage supply voltage.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I
SENSE
SYNC
FF
UV
OV
R
T
/C
T
I
SET
V
FB
COMP
SS
LGnd
V
REF
V
CC
PGnd
V
C
Block Diagram
V
CC
3.3V
UVL
ENABLE
2mA(maximum load current)
V
REF
VREF = 3.3V
3.1V
V
REF
OK
Thermal
Shutdown
+
-
UV Lockout
Start/Stop
S
Q
G1
Low
Sat
Gate
Driver
V
C
GATE
13.5V
SYNC
R
T
C
T
3.0V
OSC
2V to 1V Trip Points
G2
R
Q
Max Duty Cycle
(Sat Sense)
SS to 1.8V Max
PGnd
V
BG
(1.263V) EAMP
V
REF
50µA
V
FB
COMP
Soft Start Clamp
PWM
Comp
LGnd
FF
FF Discharge
ON
V
O
Off
G
3
Max SS
Det
G4
OV Monitor
Latching
Discharge
5µA
SS
I
SET
I
LIM
DISABLE
150ns
Blank
(Sat Sense)
OV
3.0V
2V
UV Monitor
UV
1V
I
SENSE
6
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
