CS5132
Absolute Maximum Ratings
Pin Symbol
V
CC1
V
CC2
COMP1, COMP2
Pin Name
IC Logic and Low Side Driver Power Input
IC High Side Drivers Power Input
Compensation Pins for the V
CORE
and V
I/O
error amplifiers.
V
MAX
16V
16V
6V
V
MIN
-0.3V
-0.3V
-0.3V
I
SOURCE
N/A
N/A
1mA
I
SINK
1.5A Peak
200mA DC
3A Peak
400mA DC
5mA
V
FB1
, V
OUT1
, V
ID0-4
, V
CORE
Voltage Feedback Input Pin,
V
OUT2
, V
FB2
, V
FFB1
, V
CORE
Output Voltage Sense Pin,
V
FFB2
Voltage ID DAC Input Pins, V
I/O
Output Voltage
Sense Pin, V
I/O
Voltage Feedback Input Pin,
V
CORE
PWM comparator Fast Feedback Pin, V
I/O
PWM comparator Fast Feedback Pin.
C
OFF1
, C
OFF2
GATE(H), GATE
Off-Time Pins for the V
CORE
and V
I/O
regulators
High-Side FET Drivers for the V
CORE
and V
I/O
regulators.
Low-Side FET Driver
Power-Good Output
Overvoltage Protection
Power Ground
6V
-0.3V
1mA
1mA
6V
16V
-0.3V
-0.3V
1mA
1.5A Peak
200mA DC
1.5A Peak
200mA DC
1mA
30mA
3A Peak
400mA DC
40mA
50mA
1.5A Peak
200mA DC
1.5A Peak
200mA DC
30mA
1mA
N/A
GATE(L)
PWRGD
OVP
PGnd
16V
6V
15V
0V
-0.3V
-0.3V
-0.3V
0V
LGnd
Logic Ground
0V
0V
N/A
Operating Junction Temperature, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 125¡C
Lead Temperature Soldering:
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 sec max. above 183ûC, 230ûC Peak
Storage Temperature Range, T
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150ûC
ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
23,24,1,2,3
V
IDO
Ð V
ID4
20
17
18
19
16
15
21
22
V
CC1
GATE(H)
PGnd
GATE(L)
V
CC2
GATE
OVP
PWRGD
Voltage ID DAC inputs. These pins are internally pulled up to 5.65V if
left open. V
ID4
selects the DAC range. When V
ID4
is high (logic one),
the Error Amp reference range is 2.125V to 3.525V with 100mV incre-
ments. When V
ID4
is low (logic zero), the Error amp reference voltage
is 1.325V to 2.075V with 50mV increments.
Input power supply pin for the internal circuitry, and low side gate
driver. Decouple with filter capacitor to PGnd.
High side switch FET driver pin for V
CORE
section.
Power ground for V
CORE
and V
I/O
section.
Low side synchronous FET driver pin.
Input power supply pin for on-board high side gate drivers. Decouple
with filter capacitor to PGnd.
High side switch FET driver pin for V
I/O
section.
Overvoltage protection pin. Goes high when overvoltage condition is
detected on V
FB1
.
Power-Good Output. Open collector output drives low when V
FB1
is
out of regulation.
2
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
