CS5210-1
Application Notes: continued
Theory of Operation
The CS5210-1 linear regulator has a composite PNP-NPN
output stage that requires an output capacitor for stability.
A detailed procedure for selecting this capacitor is includ-
ed in the Stability Considerations section.
Adjustable Operation
specification of 6V for the voltage difference between V
IN
and V
OUT
. However, the IC may be used to regulate volt-
ages in excess of 6V. The main considerations in such a
design are power-up and short circuit capability.
In most applications, ramp-up of the power supply to V
IN
is fairly slow, typically on the order of several tens of mil-
liseconds, while the regulator responds in less than one
microsecond. In this case, the linear regulator begins
charging the output capacitor as soon as the V
IN
to V
OUT
differential is large enough that the pass transistor con-
ducts current. V
OUT
is essentially at ground, and V
IN
is on
the order of several hundred millivolts, so that the pass
transistor is in dropout. As V
IN
increases, the pass transis-
tor will remain in dropout, and current is passed to the
load until V
OUT
is in regulation. Further increase in V
IN
brings the pass transistor out of dropout. The result is that
the output voltage follows the power supply ramp-up,
staying in dropout until the regulation point is reached. In
this manner, any output voltage may be regulated. There
is no theoretical limit to the regulated voltage as long as
the V
IN
to V
OUT
differential of 6V is not exceeded.
However, maximum ratings of the IC will be exceeded in a
short circuit condition. Short circuit conditions will result
in the immediate operation of the pass transistor outside of
its safe operating area. Over-voltage stresses will then
cause destruction of the pass transistor before overcurrent
or thermal shutdown circuitry can become active.
Additional circuitry may be required to clamp V
IN
to V
OUT
differential to less than 6V if failsafe operation is required.
One possible clamp circuit is illustrated below; however,
the design of clamp circuitry must be done on an applica-
tion by application basis. Care must be taken to ensure the
clamp actually protects the design. Components used in
the clamp design must be able to withstand the short cir-
cuit conditions indefinitely while protecting the IC.
Design Guidelines
This LDO adjustable regulator has an output voltage range
of 1.25V to 4.5V. An external resistor divider sets the out-
put voltage as shown in Figure 1. The regulatorÕs voltage
sensing error amplifier maintains a fixed 1.25V reference
between the output pin and the adjust pin.
A resistor divider network R
1
and R
2
causes a fixed current
to flow to ground. This current creates a voltage across R
2
that adds to the 1.25V across R
1
and sets the overall output
voltage. The adjust pin current (typically 50µA) also flows
through R
2
and adds a small error that should be taken
into account if precise adjustment of V
OUT
is necessary.
The output voltage is set according to the formula:
R + R
2
V
OUT
= V
REF
´
1
+ R
2
´
I
Adj
R
1
The term I
Adj
´
R
2
represents the error added by the adjust
pin current.
R
1
is chosen so that the minimum load current is a least
10mA. R
1
and R
2
should be of the same composition for
best tracking over temperature. The divider resistor
should be placed as close to the IC as possible and connect-
ed to the output with a separate metal trace.
V
IN
V
OUT
CS5210-1
Adj
EXTERNAL SUPPLY
R1
R2
V
IN
V
OUT
V
Adj
Figure 1:
While not required, a bypass capacitor connected between
the adjust pin and ground will improve transient response
and ripple rejection. A 0.1µF tantalum capacitor is recom-
mended for Òfirst cutÓ design. Value and type may be var-
ied to optimize performance vs price.
The CS5210-1 linear regulator has an absolute maximum
Figure 2:
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CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
