CS5651
Typical Performance Characteristics: continued
Reference Voltage Change vs. Source Current
0
V
CC
= 15V
∆
V
REF
, REFERENCE
Voltage (mV)
-4.0
-8.0
-12
-16
-20
-24
0
20
40
60
80
100
I
ref
, REFERENCE SOURCE CURRENT (mA)
120
T
A
= 125°C
T
A
=
25°C
Reference Short Circuit Current vs. Temperature
I
SC
, REFERENCE
SHORT CIRCUIT CURRENT (mA)
120
100
T
A
= –55°C
80
60
-55
-25
0
25
50
75
100
125
T
A
, AMBIENT TEMPERATURE (°C)
Output Saturation Voltage vs. Load Current
0
V
CC
Supply Current vs. Supply Voltage
32
I
CC,
SUPPLY CURRENT (mA)
R
T
=8.2kΩ
C
T
=3.3nF
SOURCE SATURATION
(LOAD TO GROUND)
V
sat
, OUTPUT
SATURATION VOLTAGE (V)
-1.0
-2.0
V
CC
=15V
80µS PULSED LOAD
120Hz RATE
T
A
=25°C
24
V
FB
1, 2=0V
CURRENT SENSE 1, 2=0V
T
A
=25°C
T
A
= –55°C
16
2.0
1.0
0
0
T
A
= –55°C
T
A
=25°C
GND
8.0
SINK
SATURATION
(LOAD TO V
CC
)
0
200
400
600
OUTPUT LOAD CURRENT (mA)
800
0
4.0
8.0
12
16
20
V
CC,
SUPPLY VOLTAGE (V) - CS-5651
Operating Description
The CS5651 is a high performance, fixed frequency, dual
channel current mode PWM controller for Off-Line and
DC to DC converter applications. Each channel contains a
high gain error amplifier, current sensing comparator,
pulse width modulator latch, and totem pole output driv-
er. The oscillator, reference, and undervoltage lockout cir-
cuits are common to both channels.
Oscillator
making this controller suitable for high frequency power
conversion applications.
In noise sensitive applications it may be necessary to syn-
chronize the converter with an external system clock. This
can be accomplished by applying an external clock signal.
For reliable synchronization, the oscillator frequency
should be set about 10% slower than the clock frequency.
The rising edge of the clock signal applied to SYNC, termi-
nates the charging of C
T
and V
OUT2
conduction. By tailor-
ing the clock waveform symmetry, accurate duty cycle
clamping of either output can be achieved.
Error Amplifier
The oscillator has both precise frequency and duty cycle
control. The oscillator frequency is programmed by the
timing components R
T
and C
T
. Capacitor C
T
is charged
and discharged by an equal magnitude internal current
source and sink, that generates a symmetrical 50 percent
duty cycle waveform at C
T
. The oscillator peak and valley
thresholds are 3.5V and 1.6V respectively. The source/
sink current is controlled by resistor R
T
. For proper opera-
tion over temperature range R
T
’s value should be between
4.0kΩ to 16kΩ.
As C
T
charges and discharges, an internal blanking pulse
is generated that alternately drives the inputs of the upper
and lower NOR gates high. This, in conjunction with a
precise amount of delay time introduced into each chan-
nel, produces well defined non-overlapping output duty
cycles. Output 2 is enabled while C
T
is charging, and
Output 1 is enabled during the discharge. Even at 500kHz,
each output is capable of approximately 44% duty cycle,
5
Each channel contains a fully-compensated error amplifier
with access to the output and inverting input. The amplifi-
er features a typical dc voltage gain of 100 dB, and a unity
gain bandwidth of 1.0 MHz with 71 degrees of phase mar-
gin. The non-inverting input is internally biased at 2.5V.
The converter output voltage is typically divided down
and monitored by the inverting input through a resistor
divider. The maximum input bias current is -1.0 µA which
will cause an output voltage error that is equal to the
product of the input bias current and the equivalent input
divider resistance.
Its output voltage is offset by two diode drops (≈1.4V) and
divided by three before it connects to the inverting input
of the current sense comparator. This guarantees that both
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
