CS8128
RESET Circuit Waveform
(1) = No Delay Capacitor
(2) = With Delay Capacitor
(3) = Max: RESET Voltage (1.0V)
V
OUT
V
RTH
V
RT
L
V
RH
RESET
(3)
V
RL
(1)
(2)
Delay
V
DH
V
DTC
V
DTD
T
D
(2)
V
DIS
RESET Circuit Functional Description
The CS8128 RESET function is very precise, has hysteresis
on both the RESET and Delay comparators, a latching
Delay capacitor discharge circuit, and operation down to
1V.
The reset circuit output is an open collector type with ON
and OFF parameters as specified. The reset output NPN
transistor is controlled by the Low Voltage Inhibit and
Reset Delay circuits (see Block Diagram).
Low Voltage Inhibit Circuit
RESET Delay Circuit
This circuit monitors output voltage, and when output
voltage is below V
RTL
, causes the reset output transistor to
be in the ON (saturation) state. When the output voltage is
above V
RTH
, this circuit permits the reset output transistor
to go into the OFF state if allowed by the reset Delay cir-
cuit.
This circuit provides a programmable (by external capaci-
tor) delay on the RESET output lead. The Delay lead pro-
vides source current to the external delay capacitor only
when the Low Voltage Inhibit circuit indicates that output
voltage is above V
RTH
. Otherwise, the Delay lead sinks
current to ground (used to discharge the Delay capacitor).
The discharge current is latched ON when the output volt-
age falls below V
RTL
. The Delay capacitor is fully dis-
charged anytime the output voltage falls out of regulation,
even for a short period of time. This feature ensures a con-
trolled RESET pulse is generated following the detection
of an error condition. The circuit allows the RESET out-
put transistor to go to the OFF (open) state only when the
voltage on the Delay lead is higher than V
DTC
.
4
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
