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CS181002-CQ/A1 参数 Datasheet PDF下载

CS181002-CQ/A1图片预览
型号: CS181002-CQ/A1
PDF下载: 下载PDF文件 查看货源
内容描述: 数字音频网络处理器 [Digital Audio Networking Processor]
分类和应用: 消费电路商用集成电路
文件页数/大小: 54 页 / 663 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CobraNet Hardware User’s Manual  
Pinout and Signal Descriptions  
4.2.5 Miscellaneous Signals  
CM-2  
Pin #  
CS1810xx/  
CS4961xx Pin #  
Signal  
Description Direction  
Notes  
System reset (active low).  
HRESET  
Reset  
In  
J1:A18  
93  
95  
92  
10 ns max rise time. 1 ms min assertion time.  
Toggles at 750 Hz nominal rate to indicate proper  
operation. Period duration in excess of 200 ms  
indicates hardware or software failure has occurred  
and the interface should be reset. Note that  
improper operation can also be indicated by short  
pulses (<100 ns).  
WATCHDOG  
Watch Dog  
Out  
J3:A17  
Interface  
Ready  
Asserts (active low) during initialization and when a  
fault is detected or connection to the network is lost.  
MUTE  
NC  
Out  
-
J3:A2  
-
28, 50-53, 78-  
81, 141, 142  
No Connect  
4.2.6 Power and Ground Signals  
CS1810xx/CS4961xx  
Signal  
Description  
CM-2 Pin #  
Specification  
Pin #  
J1:B20, B17, B15,  
B13, B11, B9, B7,  
B5, B3  
System Digital +3.3 v  
N/A  
VCC_+3V  
3.3 0.3v, 500 mA Typ., 750 mA Max.  
J3:B14, B12, B10,  
B8, B6, B4, B2  
J3;B[18:17]  
N/A  
N/A  
Backwards Compatibility  
VCC_+5V  
10, 24, 54, 66, 83,  
98, 119, 130  
VDDD  
+1.8 V @ 500mA Typ. for Core Logic  
18, 33, 44, 60, 73,  
91, 113, 136  
VDDIO  
VDDA  
N/A  
N/A  
+3.3 V @ 120mA Typ. for I/O Logic  
Filtered +1.8 V @ 10mA Typ.  
129  
N/A  
AUX_POWER  
[3-0]  
J3:B[20:19],  
A[20:19]  
J1:B19, B16, B14,  
B12, B10, B8, B6,  
B4, B2  
13, 21, 27, 36, 47,  
57, 63, 69, 76, 86,  
94, 101, 116, 122,  
126, 133, 139  
GND  
Digital Ground  
J3:B16, B15, B13,  
B11, B9, B7, B5,  
B3, B1  
14  
©Copyright 2005 Cirrus Logic, Inc.  
DS651UM23  
Version 2.3