CS4216
SCLK*
t s2
DIx
t pd2
DOx
* SCLK is inverted for SM1 and SM2
DI/DO Timing
SCLK
SSYNC
(Master Mode)
SCLK & SSYNC Output Timing
(Master Mode)
t h2
CLKIN
t pd3
t ckl
t ckh
DIGITAL CHARACTERISTICS
(T
A
= 25°C; VA, VD = 5V)
Parameter
High-level Input Voltage
Low-level Input Voltage
High-level Output Voltage at I0 = -2.0 mA
Low-level Output Voltage at I0 = +2.0 mA
Input Leakage Current
Output Leakage Current
Output Capacitance
Input Capacitance
(Digital Inputs)
(High-Z Digital Outputs)
COUT
CIN
Symbol
VIH
VIL
VOH
VOL
Min
VD-1.0
-
VD-0.3
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
Max
-
1.0
-
0.1
10
10
15
15
Units
V
V
V
V
µA
µA
pF
pF
6
DS83F2
CIRRUS [ CIRRUS LOGIC ]
