CS4222
DSP Port Mode Byte (5)
B7
DEM2
B6
DEM1
B5
DEM0
B4
DSCK
B3
DDO
B2
DDF2
B1
DDF1
B0
DDF0
DEM2-0
Selects de-emphasis control source
0 - De-emphasis controlled by pins
1 - 44.1 kHz de-emphasis setting
2 - 48 kHz de-emphasis setting
3 - 32 kHz de-emphasis setting
4 - De-emphasis disabled
5, 6, 7 - Not used
DSCK
Sets the polarity of clocking data for both input and output
0 - Data valid on rising edge of SCLK
1 - Data valid on falling edge of SCLK
Data output format
0 - I
2
S compatible
1 - Left justified
Data input format
0 - I
2
S compatible
1 - Left justified
2 - Right justified, 20-bit
3 - Right justified, 18-bit
4 - Right justified, 16-bit
5, 6, 7 - Not used
DDO
DDI2-DDI0
This register defaults to 00h.
Converter Status Report Byte (Read Only) (6)
B7
ACCR
B6
ACCL
B5
LVR2
B4
LVR1
B3
LVR0
B2
LVL2
B1
LVL2
B0
LVL0
ACCR-ACCL
Acceptance bit
0 - ATT7-0 has been accepted
1 - New setting waiting for zero crossing
Left and Right ADC output level
0 - Normal output levels
1 - -6 dB level
2 - -5 dB level
3 - -4 dB level
4 - -3 dB level
5 - -2 dB level
6 - -1 dB level
7 - Clipping
LVL2-0,LVR2-0
LVL2-0 and LVR2-0 bits are 'sticky'. They constantly monitor the ADC output for the peak levels and hold the max-
imum output. They are reset to 0 when the
DSP Port Mode Byte (5)
is read.
This register is read only.
DS236F1
27
CIRRUS [ CIRRUS LOGIC ]
